sarang5s5
Newbie level 5
What is the meaning of hierarchical boundaries in a design netlist or schematic generated after synthesis?
After synthesizing an RTL design (Verilog or VHDL or System Verilog) containing sub-modules, the gate-level netlist gets generated.
Is the hierarchical boundary similar to module or instance ports ?
If not, what exactly is the hierarchical boundaries in the design or schematic ?
After synthesizing an RTL design (Verilog or VHDL or System Verilog) containing sub-modules, the gate-level netlist gets generated.
Is the hierarchical boundary similar to module or instance ports ?
If not, what exactly is the hierarchical boundaries in the design or schematic ?
