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  1. #1
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    System verilog - streaming operator multidimensional array to stream of bits

    Hi guys,
    I cant figure out how to take multidimensional array such as:

    bit unsigned [10:0] img [3:0][3:0];

    And make this array as a stream of bits. Think of it as an 4X4 image that each pixel is 11 bits in my memory that I want to read, and I have 1 input pin that get my image as a stream of bits, I prefer if you have any idea how to do that, to get the data in streams of 11 bits (lets say I have a typedef). I want to declare an array like this in the testbench, and send this array as a stream of bits to my module that I want to test.
    I'm working with quartus2 and with modelsim-sltera simulator.

    I tried to do any variation i saw online, but nothing useful:

    stream = { >> {img}};
    or

    stream = { << {img}};

    defined stream as bits or int , exc.

    edit: the errors I got from the above attempts were identical:

    "near text ">>"; expecting an operand"

    Thanks a lot for any help.

    - - - Updated - - -

    sorry, I missed the fact that it is analog forum Ill be happy if this post will pass to the right forum.

    •   Alt7th March 2018, 13:56

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  2. #2
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    Re: System verilog - streaming operator multidimensional array to stream of bits

    Since this is for a testbench why not use a nested for loop with a time control statement in the inner loop to serially output the bits.

    Just checked and the streaming operator is not used like you are showing it's on the wrong side of the assignment to begin with and it's not for generating a stream of bits.
    see this


    1 members found this post helpful.

    •   Alt7th March 2018, 17:43

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  3. #3
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    Re: System verilog - streaming operator multidimensional array to stream of bits

    that is a nice idea Ill try to implement .
    And no its not.. http://www.asic-world.com/systemverilog/operators6.html
    Thanks



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