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    how to program adxl345 on DE10-Lite in verilog?

    hello all,
    as the title, I'm trying to read the device ID of adxl345 on my board in 4-wire SPI, but I have some problems, I get the wrong device ID (every bit is one).
    The following is my code, and I don't kwon where I make mistakes. Can anyone tell where I make mistakes and how to get the correct device ID?

    Code:
    module sensor(sw0,clk,hex0,sdo,sdi,cs,sclk);
    
    input sw0,clk;
    output [7:0] hex0;
    
    input sdo;
    output cs,sdi,sclk;
    
    
    reg cs,next_cs;
    reg sclk_ctrl,next_sclk;
    reg sdi,next_sdi;
    reg [7:0] address;
    reg [7:0] data,next_data;
    reg [3:0] cnt,next_cnt;
    reg [2:0] state,next_state;
    
    pll p0(
    	.inclk0(clk),
    	.c0(clk2)
    	);
    	
    assign sclk=(sclk_ctrl)?clk2:1'b1;
    assign hex0=(cs)?data:8'd255;
    
    always @(negedge clk2) begin
    	if(sw0) begin
    		state<=next_state;
    		cs<=next_cs;
    		sclk_ctrl<=next_sclk;
    		cnt<=next_cnt;
    	end
    	else begin
    		state<=3'd0;
    		cs<=1'b1;
    		sclk_ctrl<=0;
    		cnt<=4'd15;
    		address<=8'b10000000;
    	end
    end
    
    always @(posedge clk2) begin
    	if (sw0) begin
    		sdi<=next_sdi;
    		data<=next_data;
    	end
    	else begin
    		sdi<=1'b0;
    		data<=8'd0;
    	end
    end
    
    always @(*) begin
    	case (state)
    		3'd0:		begin
    						next_state=(sw0)?3'd1:3'd0;
    						next_cs=1'b0;
    						next_sclk=1'b0;
    						next_cnt=4'd15;
    						next_sdi=1'b0;
    						next_data=data;
    					end
    		3'd1:		begin
    						next_state=3'd2;
    						next_cs=1'b0;
    						next_sclk=1'b1;
    						next_cnt=4'd15;
    						next_sdi=1'b0;
    						next_data=data;
    		end
    		3'd2:		begin
    						next_state=(cnt==8)?3'd3:3'd2;
    						next_cs=1'b0;
    						next_sclk=1'b1;
    						next_cnt=cnt-8'd1;
    						next_sdi=address[cnt-8'd8];
    						next_data=data;
    					end
    		3'd3:		begin
    						next_state=(cnt==0)?3'd4:3'd3; 
    						next_cs=1'b0;
    						next_sclk=1'b1;
    						next_cnt=cnt-8'd1;
    						next_sdi=1'bx; 
    						next_data={data[6:0],sdo}; 					
    					end
    		3'd4:		begin
    						next_state= 3'd5; 
    						next_cs=1'b0;
    						next_sclk=1'b0;
    						next_cnt=cnt;
    						next_data=data; 
    					end
    		3'd5:		begin
    						next_state=(sw0)?3'd5:3'd0; 
    						next_cs=1'b1;
    						next_sclk=1'b0;
    						next_cnt=cnt;
    						next_data=data; 
    					end
    					
    		default:	begin
    						next_state=(sw0)?3'd1:3'd0;
    						next_cs=1'b1;
    						next_sclk=1'b0;
    						next_cnt=4'd15;
    						next_sdi=1'b0;
    						next_data=8'd0;
    					end
    	endcase
    end
    
    endmodule Attachment 145115
    and this is the result(using signal tap)
    Click image for larger version. 

Name:	2018-03-05 (1).png 
Views:	6 
Size:	128.4 KB 
ID:	145116

    thanks
    Last edited by adam9; 5th March 2018 at 12:11.

  2. #2
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    Re: how to program adxl345 on DE10-Lite in verilog?

    Didn't look at the design, just the SPI waveforms.

    According to the datasheet, your SPI signal timing is wrong. Mode 3 is expected. SDI must be set before the rising clock edge, usually it's already set at the falling edge.



    •   Alt5th March 2018, 12:06

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  3. #3
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    Re: how to program adxl345 on DE10-Lite in verilog?

    Did you mean like this? But I still have the same problem
    Click image for larger version. 

Name:	螢幕截圖 2018-03-05 21.13.37.png 
Views:	7 
Size:	112.3 KB 
ID:	145120



    •   Alt5th March 2018, 14:15

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    Re: how to program adxl345 on DE10-Lite in verilog?

    Yes, correct SDI timing now. But is it a valid read command?



    •   Alt5th March 2018, 19:32

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    Re: how to program adxl345 on DE10-Lite in verilog?

    Quote Originally Posted by FvM View Post
    Yes, correct SDI timing now. But is it a valid read command?
    According to the datasheet, if I didn't misunderstanding it, when the first bit of SDI is one, it's in read mode. So I think it's a valid read command



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    Re: how to program adxl345 on DE10-Lite in verilog?

    Hi,

    Im confused because the PLD should be the master of the SPI, but SDI (Serial Data In) seems to be an output... and the same is with SDO.
    This seems to be the signal name of the slave...
    Please refer to the name of the signals on the processor side (your PLD) of figure 35.

    To avoid confusions I recommend to use SPI typical names like "MOSI" and "MISO", which are self explaining.

    Additinaly I recommend to insert some comments into your code. This will motify more members to go through your code ... and it it will help yourself if you rtry to read the code in a couple of years.

    Im not familiar with verilog, but I cant find data(7)..
    All in all I find the code rather complicated for those simple shift operations of an SPI interface.

    Klaus
    Please dont contact me via PM, because there is no time to respond to them. No friend requests. Thank you.



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    Re: how to program adxl345 on DE10-Lite in verilog?

    Quote Originally Posted by KlausST View Post
    Hi,

    Im confused because the PLD should be the master of the SPI, but SDI (Serial Data In) seems to be an output... and the same is with SDO.
    This seems to be the signal name of the slave...
    Please refer to the name of the signals on the processor side (your PLD) of figure 35.

    To avoid confusions I recommend to use SPI typical names like "MOSI" and "MISO", which are self explaining.

    Additinaly I recommend to insert some comments into your code. This will motify more members to go through your code ... and it it will help yourself if you rtry to read the code in a couple of years.

    Im not familiar with verilog, but I cant find data(7)..
    All in all I find the code rather complicated for those simple shift operations of an SPI interface.

    Klaus
    Thank you for your advice! But I still don't know where I make mistakes



    •   Alt7th March 2018, 18:08

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    Re: how to program adxl345 on DE10-Lite in verilog?

    Hi,

    Verifying your application is difficult.
    This is because there are no comments in your code, thus we need to spend much time to find out what you want to do with each step.

    And then we don't know nothing about how you connected the PLD with the sensor.
    We don't know which pin is connected to which pin,
    We don't know about interface timing
    We don't know about voltage levels, nor power supplies

    Therefore I recommend:
    Please post your IO configuration file and
    please post your real schematic and
    Please post a real scope picture of the signals.

    Then we are able to verify the complete chain.

    Klaus
    Please dont contact me via PM, because there is no time to respond to them. No friend requests. Thank you.



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    Re: how to program adxl345 on DE10-Lite in verilog?

    Given you are using a gated clock to generate SCLK from an FSM running off of CLK.

    And appear to be using a PLL to generate what looks to be a 2x multiplied clock.

    Given that I've never run across an FPGA PLL that can run at less than 10-15 MHz input clock frequencies, you must be generating a 2x clock of at least 20 MHz or more.

    The part (ADXL345) you are communicating with requires a clock period of 200 ns or 5 MHz so to do what you are trying CLK must be only 2.5 MHz or slower.

    Given what I could glean from the circumstantial evidence I would guess that is your problem. You are probably running the SPI way beyond spec.

    BTW the design as implemented with: no comments, gated clock, two always block FSM, lack of parameters (or enumerated state names in SV), and not using normal if statements for the branch conditions just makes your code less readable (maintainable) and longer than required.

    This interface should be no more than a 50 line file with nearly half of those lines being comments.


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