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  1. #1
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    Compare vectors with threshold

    hi all

    i'v 2 std vectors (16 bit wide) and i need to compare them within threshold (4 bit wide).

    Code:
    enable	 <= '1' when unsigned(DATA) <= ((DATA2)+("0000"&unsigned(THRESHOLD))) and 
                                       unsigned(DATA) >= ((DATA2)-("0000"&unsigned(THRESHOLD))) else	  
    		       '0' ;
    i know there is a problem on the edges of the vector, for example:

    2>= 0-7

    any suggestion would be aprochiated


    Best
    Gil

    •   Alt25th February 2018, 15:28

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  2. #2
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    Re: Compare vectors with threshold

    I dont really understand the problem. Please could you explain what the issue is. Your code sets enable to '1' when DATA is between the THRESHOLD values on DATA2.

    NOTE. Why is everything declared as std_logic_vector, and not unsigned? doing all these type conversions makes it harder to read and may end up giving you an RSI.



    •   Alt25th February 2018, 17:43

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  3. #3
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    Re: Compare vectors with threshold

    I dont really understand the problem. Please could you explain what the issue is. Your code sets enable to '1' when DATA is between the THRESHOLD values on DATA2.
    the problem is with negative numbers, for example:
    DATA = 4,
    DATA2 = 2
    THRESHOLD = 5



    •   Alt27th February 2018, 15:01

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  4. #4
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    Re: Compare vectors with threshold

    Your problem is one of wrap around. The 2nd compare will wrap around to a very high unsigned number.
    Why not used the signed type instead to avoid this problem?



  5. #5
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    Re: Compare vectors with threshold

    Do you mean somthing like this:

    Code:
    enable <= '1' when unsigned(abs(signed(DATA)-signed(DATA2)) < ("0000"&unsigned(THRESHOLD)) else '0'  ;



    •   Alt27th February 2018, 15:19

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  6. #6
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    Re: Compare vectors with threshold

    Thats pretty hiddeous. WHats wrong with this:

    Code VHDL - [expand]
    1
    2
    3
    
    enable   <= '1' when signed('0' & DATA) <= (signed('0' & DATA2)+(signed('0' & THRESHOLD))) and 
                         signed('0' & DATA) >= (signed('0' & DATA2)-(signed('0' & THRESHOLD))) else   
                   '0' ;

    Would be even better if DATA, DATA2 and THRESHOLD are signed data types in the first place. There is absolutly no need for them to be std_logic_vectors. Ports can be unsigned/signed.


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  7. #7
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    Re: Compare vectors with threshold

    Hi

    i'v changed it so it can do the warp around:
    Code:
    enable_riz	 		<= '1' when resize(signed(COMPA),COMPA'length +2)   <= (resize(signed(COMPB),COMPB'length +2)  +(signed('0' & th))) and 
    								resize(signed(COMPA),COMPA'length +2)   >= (resize(signed(COMPB),COMPB'length +2)  -(signed('0' & th)))
    						   else '0' ;
    your code is:
    Code:
    enable   	<= '1' when signed('0' & COMPA) <= (signed('0' & COMPB)+(signed('0' & th))) and 
    							signed('0' & COMPA) >= (signed('0' & COMPB)-(signed('0' & th))) 
    					   else '0' ;
    and the results are:

    Click image for larger version. 

Name:	comp.jpg 
Views:	3 
Size:	161.0 KB 
ID:	145107



  8. #8
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    Re: Compare vectors with threshold

    What is your question? You have only posted a snippet and a waveform with different signal names to what is in your code.
    Please ask a question and post the whole code if you have an issue.



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