+ Post New Thread
Results 1 to 5 of 5
  1. #1
    Member level 5
    Points: 818, Level: 6

    Join Date
    Feb 2017
    Posts
    93
    Helped
    0 / 0
    Points
    818
    Level
    6

    SystemVerilog assertions in the place of DFT?

    Hello,

    while i'm reading about sv assertions. i found that these are synthesizable and in silicon too. Makes the debug time lesser.

    If this is the case, can we use SVA in place of DFT ?

    one more question is, "SVA is used for temporal domain coverage". plz explain this.
    I heard about code and functional coverage .

    •   AltAdvertisement

        
       

  2. #2
    Advanced Member level 5
    Points: 8,683, Level: 22

    Join Date
    Apr 2016
    Posts
    1,823
    Helped
    320 / 320
    Points
    8,683
    Level
    22

    Re: SystemVerilog assertions in the place of DFT?

    Quote Originally Posted by hcu View Post
    Hello,

    while i'm reading about sv assertions. i found that these are synthesizable and in silicon too. Makes the debug time lesser.

    If this is the case, can we use SVA in place of DFT ?

    one more question is, "SVA is used for temporal domain coverage". plz explain this.
    I heard about code and functional coverage .
    1 - no. very different goals.
    2 - weird phrasing. not sure what the author meant. temporal instead of spatial?
    Really, I am not Sam.



    •   AltAdvertisement

        
       

  3. #3
    Advanced Member level 3
    Points: 6,510, Level: 19
    Achievements:
    Created Blog entry 7 years registered

    Join Date
    Dec 2011
    Location
    Fremont, CA, USA
    Posts
    788
    Helped
    355 / 355
    Points
    6,510
    Level
    19
    Blog Entries
    4

    Re: SystemVerilog assertions in the place of DFT?

    Design for Test(DFT) is technology used to confirm that a manufactured part is implemented as you instructed. It is used to check manufacturing process failures. It does nothing to check that the instructions meet the requirements of what you were asked to design.

    SVA checks that your design satisfies a requirement. e.g. "A request for data must respond within 5 clock cycles" The syntax used with SVA is best suited for protocol checking and state transitions over time - that is called temporal. It is not as well suited for checking validity of data, like a compression algorithm. You will have to write a reference model that predicts what the data should be and checks that by comparing with the actual data. Both SVA and the checkers you write contribute to functional coverage of your requirements.

    Code coverage measures whether a test, or a set of tests exercises your RTL code. You can assume that unexercised code is untested or unused functionality, but you cannot assume exercised code is functionally correct.
    Dave Rich
    Senior Verification Consultant
    Mentor Graphics Corporation


    1 members found this post helpful.

    •   AltAdvertisement

        
       

  4. #4
    Member level 5
    Points: 818, Level: 6

    Join Date
    Feb 2017
    Posts
    93
    Helped
    0 / 0
    Points
    818
    Level
    6

    Re: SystemVerilog assertions in the place of DFT?

    Quote Originally Posted by dave_59 View Post
    Design for Test(DFT) is technology used to confirm that a manufactured part is implemented as you instructed. It is used to check manufacturing process failures. It does nothing to check that the instructions meet the requirements of what you were asked to design.

    SVA checks that your design satisfies a requirement. e.g. "A request for data must respond within 5 clock cycles" The syntax used with SVA is best suited for protocol checking and state transitions over time - that is called temporal. It is not as well suited for checking validity of data, like a compression algorithm. You will have to write a reference model that predicts what the data should be and checks that by comparing with the actual data. Both SVA and the checkers you write contribute to functional coverage of your requirements.

    Code coverage measures whether a test, or a set of tests exercises your RTL code. You can assume that unexercised code is untested or unused functionality, but you cannot assume exercised code is functionally correct.
    Code:
     It is used to check manufacturing process failures. SVA checks that your design satisfies a requirement.
    I thought using sva in the place of LBIST.
    whats the purpose of taking SVA into hardware emulation and into the silicon particularly even after verification signoff.



  5. #5
    Advanced Member level 5
    Points: 8,683, Level: 22

    Join Date
    Apr 2016
    Posts
    1,823
    Helped
    320 / 320
    Points
    8,683
    Level
    22

    Re: SystemVerilog assertions in the place of DFT?

    Quote Originally Posted by hcu View Post
    Code:
     It is used to check manufacturing process failures. SVA checks that your design satisfies a requirement.
    I thought using sva in the place of LBIST.
    whats the purpose of taking SVA into hardware emulation and into the silicon particularly even after verification signoff.
    for emulation the answer is simple: it runs faster than simulation.
    for silicon the answer is fuzzy. the generic answer is no one should be doing it, but I can think about some online monitoring scenarios where it could be a good fit -- still a niche application though.
    Really, I am not Sam.


    1 members found this post helpful.

--[[ ]]--