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layout automatically generation

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shanmei

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I have some digital schematic( not verilog/VHDL), and I want to generate the layout automatically. The wires of each devices should be connected well when the layout is generated.

Is that possible? How to do it? Thanks.
 

Many tools have schematic driven layout but in the
cases I've been exposed to, this is really more of a
"schematic driven stupid placement plus a tangled
up mess of flight-lines".

The schematic source may or may not be what your
layout tool (=?) can do anything with. And translation
between tools is kind of a tar pit.
 
Thanks for your reply.

My version is virtuoso 6.1.6. I found that the layout GXL from this version can do the auto layout.


1. Is there any documents describing the flow?

2. For the GXL layout, I don't need the software ENCOUNTER DIGITAL IC DESIGN PLATFORM, right?

Thanks.
 

My version is virtuoso 6.1.6. I found that the layout GXL from this version can do the auto layout.
1. Is there any documents describing the flow?
Somewhere in your PDK docu. Search for it - I don't have your Virtuoso version.

2. For the GXL layout, I don't need the software ENCOUNTER DIGITAL IC DESIGN PLATFORM, right?
I don't think so. This is an alternative solution.
 
I have some digital schematic( not verilog/VHDL), and I want to generate the layout automatically. The wires of each devices should be connected well when the layout is generated.

Is that possible? How to do it? Thanks.

If you have the schematic captured, then you have a netlist! And it's READY for (digital) physical design! Using virtuoso or some combination of custom layout tool would be ridiculously naive.
 

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