cesarxhc
Newbie level 1
How to write in verilog and/or system verilog a normally open switch with delays with the following functionality: when pressed once it outputs 1 and stays 1 when depressed, when pressed a second time it outputs 0 and stays 0 when depressed. The 1 output is instantaneous upon pressing, the 0 output only occurs if the button is pressed for a determined time. This is essentially how the power button in desktops work: if computer is off pressing the button starts the computer but, if the computer is on, the button requires to be pressed for several seconds.