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    Coditional adding VHDL modules to synthesis - like using C/C++ preprocessor (ISE Xili

    Hello,

    I would like to ask one question concerning conditional adding VHDL/Verilog modules to "ISE Webpack" project. I would like to achvieve similiar effect like using C language pre-processor to define symbol and adding code to compilation based on this symbol value. I mean something like this (in C language):

    Code:
    #define DEBUG
    ...
    ...
    ...
    #ifdef DEBUG
    # include <stdio.h>
       std::cout << "[RE_words] " << re << std::endl;
       ... further code to include and compilation
    #endif
    I need such feature for debbuging purpose of VHDL project. I have external LCD display connected to my FPGA circiut by UART. In debbuging mode I want have possibility of sending messages to display from FPGA. In "Release" mode I don't need modules implementing UART on FPGA side to economize resources using.

    Could someone of more experienced colleagues point me a solution to my problem
    or give me a hint where to look for ?

    Kind Regards

    •   Alt8th January 2018, 11:05

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    Re: Coditional adding VHDL modules to synthesis - like using C/C++ preprocessor (ISE

    Read about VHDL generate statement.

    Code VHDL - [expand]
    1
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    deb1:
    if debug = 1 generate
      -- conditional code
    end generate;


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    •   Alt8th January 2018, 11:37

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    Re: Coditional adding VHDL modules to synthesis - like using C/C++ preprocessor (ISE

    Hello,

    thanks for hint, I will.

    Regards



    •   Alt8th January 2018, 11:42

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    Re: Coditional adding VHDL modules to synthesis - like using C/C++ preprocessor (ISE

    Quote Originally Posted by FvM View Post
    Read about VHDL generate statement.

    Code VHDL - [expand]
    1
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    deb1:
    if debug = 1 generate
      -- conditional code
    end generate;
    Hello,

    I am not sure if I understood this construct properly?
    I found such example (on Xilinx forum):
    usually_do: if (I=1) generate
    -- This corresponds with the actual outlook of difficultsubcomponent when extra_debug is unset
    instn : entity work.difficultsubcomponent
    port map (
    foo => foo,
    bar => bar
    )
    end generate usually_do;

    when_in_trouble: if (I=2) generate
    -- This corresponds with the actual outlook of difficultsubcomponent when extra_debug is set
    instd : entity work.difficultsubcomponent
    port map (
    foo => foo,
    bar => bar,
    baz => baz
    )
    end generate when_in_trouble;
    Depending of logical condition this code choose one of two versions of component. My question is: Does these two versions of components be synthetised on FPGA?
    I understand that only one version be used, but I am not sure if two of them will be using FPGA resources. What about a case if I do not want at all using component depending of logical condition?

    Maybe there are different tools in Xilinx ISE to achive described efect? I am wonedring if using TCL script can solve my problem, or maybe diffrent ISE tool I am not aware?

    Thanks in advance,
    FlyingDutch
    Last edited by FlyingDutch; 10th January 2018 at 09:24.



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    Re: Coditional adding VHDL modules to synthesis - like using C/C++ preprocessor (ISE

    I haven't used ISE for a long time but VHDL generate statements works perfectly in Vivado.

    Code:
    label_gen: if (I=1) generate
    -- This corresponds with the actual outlook of difficultsubcomponent when extra_debug is unset
    instn : entity work.difficultsubcomponent
    port map (
    foo => foo,
    bar => bar
    );
    
    elsif I=2 generate
    -- This corresponds with the actual outlook of difficultsubcomponent when extra_debug is set
    instd : entity work.difficultsubcomponent
    port map (
    foo => foo,
    bar => bar,
    baz => baz
    );
    end generate label_gen;
    My question is: Does these two versions of components be synthetised on FPGA?
    If I is a generic which has a fixed value at compile time, then yes two versions of synth code will be generated, depending on the value of I. Note that if I has a value other than 1 or 2, nothing will be generated.
    .....yes, I do this for fun!


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    Re: Coditional adding VHDL modules to synthesis - like using C/C++ preprocessor (ISE

    Quote Originally Posted by FlyingDutch View Post
    Depending of logical condition this code choose one of two versions of component. My question is: Does these two versions of components be synthetised on FPGA?
    I understand that only one version be used, but I am not sure if two of them will be using FPGA resources. What about a case if I do not want at all using component depending of logical condition?
    Generate statements that aren't active will not consume any resources in the FPGA. They will have the same effect as the #ifdef you asked for, but syntax checking may be executed.


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    •   Alt10th January 2018, 11:08

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    Re: Coditional adding VHDL modules to synthesis - like using C/C++ preprocessor (ISE

    Generate statements do NOT depend on the logical state of the code. The Generate conditions are set at elaboration time (ie. before synthesis/at time 0) and so will be set in stone for the design. Some compilers (I know quartus used to) will just ignore anything inside a generate where the condition is false, so you can have illegal code and syntax errors inside and you wont even get a warning, as the compiler wont even bother to look at it (this might not be the case any more). Modelsim SHOULD compile everything (but only elaborate what is necessary).

    A generate is not like an if statement. Inside a generate you can put whole blocks of code (like processes, instantiations) that will only exist in the design if the generate condition is true.


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    Re: Coditional adding VHDL modules to synthesis - like using C/C++ preprocessor (ISE

    As far as I'm aware of, Quartus flags out any syntax errors in inactive generate blocks. You particularly need to have all instantiated components in the actual work lib and all used signals defined.



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