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    irrational clk period

    Hi evryone

    I need to simulate 73Mhz clock, 50% DC, then i wrote this procedure:
    Code:
    procedure cgen(signal clk : out std_logic; constant FREQ : real) is
    constant P: time := 1 sec / FREQ;        
    constant HIGH_T : time := P/ 2;          
    constant LOW_T  : time := P- HIGH_T;  
    begin
       loop
       clk <= '1';
       wait for HIGH_T;
       clk <= '0';
       wait for LOW_T;
       end loop;
    end procedure;
    The output for it is round number, any suggestions for simulate 73Mhz clock

    Best
    Gil

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    Re: irrational clk period

    Hi,

    The output of what is a rounded number?

    Rounded timing? To an integer value seems to be impossible because 0.00000x will become 0.
    Rounded frequency to an integer seems not to be the case, too, because it will give 73000000.

    I don't know what's the problem.

    Klaus
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    Re: irrational clk period

    Let me rephrase my question.

    Is it possible to simulate clk with iritional period ? if so how will you simulate 73Mhz

    Gil



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    Re: irrational clk period

    1. P can be only accurate according to the simulation time resolution in effect. It can be adjusted in wide range.

    2. It's not clear if and why you need the 73 MHz frequency to be exact, and which error would be acceptable. The only understandable reason I can imagine is that you want to implement a certain clock frequency ratio.

    3. To realize an exact average frequency with limited time resolution, consider a DDS approach.



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    Re: irrational clk period

    What are you simulating that needs such a precise clock in simulation?
    I dont usually need anything other than 100mhz, as using this frequency make it easy to measure the number of clocks between events.



    •   Alt31st December 2017, 18:09

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    Re: irrational clk period

    2. It's not clear if and why you need the 73 MHz frequency to be exact, and which error would be acceptable. The only understandable reason I can imagine is that you want to implement a certain clock frequency ratio
    What are you simulating that needs such a precise clock in simulation?
    I do need it for communicating with a custom asic that runs at 73Mhz that do encryption.
    So what is the syntex for running 73Mhz on simulation?
    Last edited by nsgil85; 4th January 2018 at 10:16.



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    Re: irrational clk period

    Quote Originally Posted by nsgil85 View Post
    I do need it for communicating with a custom asic that runs at 73Mhz that do encryption.
    So what is the syntex for running 73Mhz on simulation?
    It's simulation. Clock frequency doesn't matter. It's all virtual.
    Really, I am not Sam.



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    Re: irrational clk period

    Quote Originally Posted by ThisIsNotSam View Post
    It's simulation. Clock frequency doesn't matter. It's all virtual.
    Have you ever done timing simulation?



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    Re: irrational clk period

    Quote Originally Posted by barry View Post
    Have you ever done timing simulation?
    ... pleeease.

    OP is clueless. He is not doing timing simulation. He is either trying to implement a 73MHz clock and doesn't know how to code an SDC file or he is doing functional simulation.
    Really, I am not Sam.



    •   Alt4th January 2018, 23:47

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    Re: irrational clk period

    Although it's probably useless, you can make the clock as accurate as you want. But apparently the OP has no idea about the required precision.



    •   Alt4th January 2018, 23:58

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    Re: irrational clk period

    Quote Originally Posted by barry View Post
    Have you ever done timing simulation?
    No - and havent needed to in 15 years.
    No need for one with a good RTL testbench and proper SDC.



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    Re: irrational clk period

    The OP just wants to generate a 73MHz signal as accurately as possible with 50% DC. He will use it for simulation. Thats it I think.
    .....yes, I do this for fun!



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    Re: irrational clk period

    Quote Originally Posted by nsgil85 View Post
    I do need it for communicating with a custom asic that runs at 73Mhz that do encryption.
    So what is the syntex for running 73Mhz on simulation?
    What is the time resolution for your simulator ?



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    Re: irrational clk period

    Saying as accurate as possible is another word for mental laziness, I think. Industry standard simulators, e.g. have configurable time resolution, it's no problem to chose 1 ps if required. Using default 1 ns resolution gives still only 2 % error (period 14 ns instead of 13.7 ns) , should be usually sufficient.



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    Re: irrational clk period

    Hi guys,

    The OP just wants to generate a 73MHz signal as accurately as possible with 50% DC. He will use it for simulation. Thats it I think.
    Correct,
    Sorry if I annoyed some of you but the question is very simple, I'm doing timing simulation,
    to those who asked, my acurrcy is 3 digits after the dot.

    Thanks



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    Re: irrational clk period

    Hi,

    I'm doing timing simulation,
    to those who asked, my acurrcy is 3 digits after the dot.
    Does this make sense?
    Timing is measured in s (seconds)
    So 0.001s (three digits after the dot) is just one millisecond.

    I doubt this is what you mean....

    Klaus
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    Re: irrational clk period

    1/73MHZ = 1.369 ns period



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    Re: irrational clk period

    1/73MHZ = 1.369 ns period
    Defective pocket calculator?



    •   Alt7th January 2018, 10:19

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    Re: irrational clk period

    Hi,

    If you mean 3rd digit of 1ns....
    You could simply say you want "1ps" of resolution.

    Klaus
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    Re: irrational clk period

    Defective pocket calculator?
    Yes
    Sorry but I do not understand why it is difficult to answer my question
    So what is the syntex for running 73Mhz on simulation?



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