# How to run two module in series using verilog

1. ## How to run two module in series using verilog

Hello, The following code is compiled and is working in parallel, Please help me to make these code work sequentially, i.e after stage1 counter should reset itself and starts from 0 for the stage2. The following codes has Module1- stage1 and module2-stage2.

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module stage1(
input Clk, //50 Hz clock
input x0,
input reset,
output reg y0,y1,y2,y3,y5,y7,y10,y15,
output reg stage1_done
);

reg [15:0] counter = 0;
parameter F = 50;

always@ (posedge Clk or posedge reset)
if(reset) begin
counter <= 0;
{y0,y1,y2,y3,y5,y7,y10,y15} <= 8'b00000000;
stage1_done <= 0;
end else begin
if(x0 == 1) begin
if(counter == 18*F)
stage1_done <= 1;
else begin
counter <= counter + 1;
stage1_done <= 0;
end
if(counter >= 1*F && counter < 10*F)
y0 <= 1;
else
y0 <= 0;
if(counter >= 1*F && counter < 17*F)
y1 <= 1;
else
y1 <= 0;
if(counter >= 1*F && counter < 9*F)
y2 <= 1;
else
y2 <= 0;
if(counter >= 11*F && counter < 16*F)
y3 <= 1;
else
y3 <= 0;
if(counter >= 1*F && counter < 18*F)
y5 <= 1;
else
y5 <= 0;
if(counter >= 1*F && counter < 5*F)
y7 <= 1;
else
y7 <= 0;
if(counter >= 1*F && counter < 5*F)
y10 <= 1;
else
y10 <= 0;
if((counter >= 2*F && counter < 9*F) || (counter >= 13*F && counter < 7*F))
y15 <= 1;
else
y15 <= 0;
end
end

endmodule

module stage2(
input x0,
input Clk, //50 Hz clock
input reset,
output reg y1,y3,y5,
output reg stage2_done
);

reg [15:0] counter = 0;
parameter F = 50;

always@ (posedge Clk or posedge reset)
if(reset) begin
counter <= 0;
{y1,y3,y5} <= 3'b000;
stage2_done <= 0;
end
else begin   if(x0 == 1) begin
if(counter == 8*F)
stage2_done <= 1;
else begin
counter <= counter + 1;
stage2_done <= 0;
end
if(counter >= 1*F && counter < 8*F)
y1 <= 1;
else
y1 <= 0;
if(counter >= 1*F && counter < 8*F)
y3 <= 1;
else
y3 <= 0;
if(counter >= 1*F && counter < 8*F)
y5 <= 1;
else
y5 <= 0;
end
end

endmodule```

•

2. ## Re: How to run two module in series using verilog

Hi,

The description is a bit vague. A flow chart could help to clarify things.

I assume you need a state machine.
Read about them to find out if this is what you need.

Klaus

•

3. ## Re: How to run two module in series using verilog

They would still be "in parralell", but you would need some extra controller logic to sequence the two modules.
But why would you do this? it would be a very inefficient pipeline and half your potential throughput.

•

4. ## Re: How to run two module in series using verilog

Hi,

The module of stage 1 and stage 2 are in a flow of the process, when stage 1 is completed then stage 2 starts.

I need a solution, in which I can reset the counter value at stage 1 and reset the counter to count from zero at stage 2.

Since, I have provided the condition in which stage1_done output is high then stage 1 is completed but making counter to reset, I am confused and not able to work on it.

5. ## Re: How to run two module in series using verilog

The way you describe it, you seem to think Verilog is a programming language - it is a hardware description language. Think of each module as a chip on a circuit board - you cannot simply add and remove chips during run time. They are there all the time and the chips work by controlling the pins. The same is true of your verilog module.

6. ## Re: How to run two module in series using verilog

Hi,

I agree and I am working on it, but getting hard time to resolve.

Will surely display the code if I come up with any solution to it, in the meanwhile suggestion and solutions are most welcome.

•

7. ## Re: How to run two module in series using verilog

Originally Posted by TrickyDicky
The way you describe it, you seem to think Verilog is a programming language - it is a hardware description language. Think of each module as a chip on a circuit board - you cannot simply add and remove chips during run time. They are there all the time and the chips work by controlling the pins. The same is true of your verilog module.
I think the code is not very well written regardless of it being thought of as software or hardware. It looks like the code is starting a bunch of pulses all aligned and shutting each one off delayed from each other. I really dislike the use of begin-end in some spots and not in others, I'd rather see consist use of begin-end even when it can be left off. especially as they don't use the recommended format for an if-else without begin-end.

If you want the second FSM to start when the first is finished, then use the done signal to start the second FSM by having an IDLE state that just stays in that state until the first FSM is "done", once it signals done the second FSM exits IDLE and does whatever it needs to do. Before you ask I'm not supplying you with a code example.

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