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    Simulation time in simulation tools like ISIM/model sim

    Hi

    I just want to understand one thing that do we have any limitations on the time length for which we can run the simulation in softwares like ISIM (Xilinx) or Model sim (Libero).
    Does it depend only on the no. of signals we are tracing in the simulator or the PC RAM as well.

    Please share some insights on this.

    Thanks

    mjuneja

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    Re: Simulation time in simulation tools like ISIM/model sim

    There is no time limit on simulations. But how long it takes to run depends on your source code and what signals you are tracing in the wave window (plus also what licence you have as some simulators deliberately degrade performance for cheaper licences).

    Ive seen simulations take several hours to run just 1ms of simulation time, and others that take a few minutes for 1s of simulation. It really depends on the design, testbench and other stuff you have going on.



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    Re: Simulation time in simulation tools like ISIM/model sim

    I don't use ISIM (have moved to Vivado years ago) or Libero.
    See this thread for ISIM limitations> https://forums.xilinx.com/t5/Simulat...uot/td-p/45554

    Does it depend only on the no. of signals we are tracing in the simulator or the PC RAM as well.
    Yes it does.
    Last edited by dpaul; 5th December 2017 at 10:39.
    .....yes, I do this for fun!


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    Re: Simulation time in simulation tools like ISIM/model sim

    Another thing affecting the speed is signals vs variables.
    Variables only have immediate value, and so use far less ram and need much less processing, like a variable in C
    Signals not only store their current value, but values that need to be set in the future, the time they are updated, plus all of the attributes that change during runtime associated with signals ('event, 'transaction, 'active etc) and so need huge amount of processing.

    Wile the UUT should follow best practice and stick to signals, where possible it can be best to use variables and other programming styles (like sparse memory modelling, linked lists, pointers etc). These take a huge processing burden off the CPU. eg, with no UUT in place, I can transfer 16MB of data into and out of a RAM model over AXI4 in seconds (10ms simulation time) in a testbench, written purely in VHDL.


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    Re: Simulation time in simulation tools like ISIM/model sim

    Quote Originally Posted by TrickyDicky View Post
    Another thing affecting the speed is signals vs variables.
    Variables only have immediate value, and so use far less ram and need much less processing, like a variable in C
    Signals not only store their current value, but values that need to be set in the future, the time they are updated, plus all of the attributes that change during runtime associated with signals ('event, 'transaction, 'active etc) and so need huge amount of processing.

    Wile the UUT should follow best practice and stick to signals, where possible it can be best to use variables and other programming styles (like sparse memory modelling, linked lists, pointers etc). These take a huge processing burden off the CPU. eg, with no UUT in place, I can transfer 16MB of data into and out of a RAM model over AXI4 in seconds (10ms simulation time) in a testbench, written purely in VHDL.
    Although I have tried at many places to use variables in place of signals in the test bench, but I am not sure about that whether we can replace the signals, connecting UUT to stimulus with variable or even shared variables.



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    Re: Simulation time in simulation tools like ISIM/model sim

    If it is a simple testbench, then you're not going to notice any speed up using variables/signals. It is only going to make a difference in more complicated modelling areas.

    If you posted an example, maybe we could help?



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    Re: Simulation time in simulation tools like ISIM/model sim

    Quote Originally Posted by TrickyDicky View Post
    If it is a simple testbench, then you're not going to notice any speed up using variables/signals. It is only going to make a difference in more complicated modelling areas.

    If you posted an example, maybe we could help?
    Actually my problem got solved after using "ntrace stop;" and replacing certain signals with variables. In fact I saved lot of RAM while processing and my simulation completed the stipulated run time as well.

    But out of curiosity I asked that whether we can replace the signals, connecting UUT to stimulus with variable or even shared variables.



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