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Coding help in Verilog

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josephine1234

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where must i include the file required for readmemb command in verilog
 

Not inside any synthesizable design. So it should be in the test-bench.
 

how do i include any file in the test bench?
 

Read a good Verilog book. Search online for tutorials.
It is very basic stuff.

**broken link removed**
 

ive already gone through the site u mentioned.. thanks!
 

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