LVS Error with Mentor Calibre in hierarchy mode only, but LVS clean in Flat mode

hi everyone,

I have done a small circuit block, by utilizing power gating. So my top module have always ON module that tracks everything, and selectively powered modules.
The layout is clean at all basic levels (both hierarchical and flat mode, with no extraction violations/warnings either), but at top level I am getting LVS error when I do hierarchical based, whereas the error is not there during flat mode run. I am using V2012.1 of calibre integrated into Virtuoso.
Following is the error in hierarchy mode




I initially thought the error is due to not directly having power supply. But there is some module inside with gated power, that works well when I tried to debug by using LVS BOX on individual modules.
Could someone help? my experience with calibre is close to null.

It might be how the text is attached to nets. Verify these settings:

* Top level nets are texted properly, with Virtuoso streaming the text objects correctly to GDS.
* The top level text layer is declared as a Text Layer in the SVRF rules.
* The SVRF file isn't overriding Text Depth. It defaults to PRIMARY, and typically that works fine.

For a detailed discussion of how Calibre applies text to nets, see the Calibre Verification User's Manual (calbr_ver_user.pdf) and look for the section "Use of Text in Calibre Applications." To just interpret the rules you see in the SVRF file, look for the SVRF manual, svrf_ur.pdf. (The manuals should be in the Calibre software tree under docs.)