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MachXO2 DDR and PCLK routing issue

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juanMco

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Hello all!

I'm doing a project in which I use DDR interfaces to transmit and receive data between different FPGAs. The FPGA transmitter will send data at 125 MHz and the receiver will use 250 MHz to sample the received data.

For the project I am using the MachXO2 family of Lattice. In principle, I had thought of using an external 125 MHz oscillator to then pass it through the internal PLL and convert it to 250 MHz using the CLKOS output. My doubt is that in the datasheet it specifies that the DDR interface requires the use of a dedicated PCLK pin. I have made simulations of the code, and after trying to implement it, in the synthesis phase I get an error if I try to connect the CLKOS output of the PLL to the DDR receiver.

My question is, how can I approach this problem? Can I somehow use CLKOS from the PLL or is it impossible? Should I look for an external oscillator of 250 MHz and connect it to a PCLK pin?

Thank you very much and greetings.
 

from the MACHX02 data sheet:

"The CLKOP, CLKOS, CLKOS2, and CLKOS3 outputs can all be used to drive the MachXO2 clock
distribution network directly"

Maybe you have to connect CLKOS to a buffer, and make sure the DDR clock is connected to the clock network.
 
It seems to me that the device supports source synchronous interfaces for DDR and has built in clock delay to center the clock in the middle of the data. Have you read the following document? look for TN1203 in the DDR section.

If you go this route you don't have to use a 250 MHz clock you use the same 125 MHz clock as DDR clock and the system clock, though you will want to make sure you have a 125 MHz clock with closer to 50/50 duty cycle.
 
It seems to me that the device supports source synchronous interfaces for DDR and has built in clock delay to center the clock in the middle of the data. Have you read the following document? look for TN1203 in the DDR section.

If you go this route you don't have to use a 250 MHz clock you use the same 125 MHz clock as DDR clock and the system clock, though you will want to make sure you have a 125 MHz clock with closer to 50/50 duty cycle.

Hi,

First of all, thanks for the help.

I had read the document but I did not understand it well, thanks for the clarification. Now another question arises: What I want to do is that when receiving a data through the receiving DDR interface (one bit in a clock cycle), the FPGA has to generate a pulse of about 40 ms that is carried to an output pin of the FPGA. To detect this data from the DDR interface to generate the pulse, would not it be necessary to do a sample at 250 MHz? How could I do it without using a 250 MHz clock?
 

If you are transmitting data with a 125MHz clock, you use that same 125MHz clock to latch your data in the receiver. That's kind of the point of source-synchronous transmission. Are you using a SERDES in your design? That should make things easier.
 

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