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  1. #1
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    LVS weird problem in Cadence

    Hi,

    I have built my subcircuits and tested both schematic/layout and LVS and all are ok. However, when I combine them to make a controller bu adding them as a new component/layout, LVS always failed. I removed all pins/labels from subcircuit, LVS still fails. But, when I copied the layout of the subcircuit to the controller layout with pins removed, the LVS works and match!!! what is the main issue here? I couldn't understand what is the problem? The output file keeps reporting cross-mismatch between transistors, but with the same layout copied, this is disappears and LVS match!!

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  2. #2
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    Re: LVS wired problem in Cadence,

    Sometimes circuits with a lot of identical looking "stuff" that
    is repeated, will make LVS confused. This can be totally "luck
    of the draw", all about how it recognizes sections as it goes
    about netlisting and such.

    A layout that is the same at the polygon level, but just
    different in some way, could pass where another fails. That's
    just the breaks. A layout with pins and a layout without
    pins, falls in this situation. LVS is left to decide what the
    pin connections are, and it's OK with that - but not OK
    with pins asserted?

    Seems to me that maybe there's some pin issue or the
    schematic matches the "subcircuit" but not the "controller"
    (maybe pins, signal nets, power globals, ???). Maybe a pin
    ended up misplaced and named some net wrongly.

    You can fix it by asserting "correspondence points" (if the
    layout and schematic do indeed match) but that effort is
    a real nuisance.


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  3. #3
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    Re: LVS wired problem in Cadence,

    Attached snap shots of the output file, I can't see any issue, the only thing is Net /116 is merged with /42 which I guess not an error. Any hint?



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  4. #4
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    Re: LVS wired problem in Cadence,

    "Merged" usually means that LVS thinks these two nets
    should be one. You should go to the extracted view,
    select-by-property the two nets and see if maybe
    there is a wiring "miss" (gap, or pins that should
    connect are missing the wire to do so altogether).


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    Re: LVS wired problem in Cadence,

    What seems an issue to me is a warning about "pcapacitor" being in the netlist but not in the layout.
    "pcapacitor" and "presistor" elements are supposed to be eliminated during netlisting step - but this should be configured properly in your environment.
    These elements are added to schematic to account for parasitic elements (and for net naming purposes - where you can have several names for the same net, by inserting artificial resistors), prior to parasitic extraction.


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  6. #6
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    Re: LVS weird problem in Cadence

    Thanks all. I solved this issue by making another layout and copy some cells (which make LVS fails) without their pins, It works now.



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