rafimiet
Member level 5
I have read many questions regarding inout port in vhdl. Given the details, I am a bit hesitated to use a tristate buffer for that. Now my question is like this:
I have three components A,B,C in a hierarchy of D.
D has a signal X : STD_LOGIC_VECTOR(99 downto 0).
The bits of this vector get modified by all the three components (A,B,C) at different times (Not simultaneously). But each component may change 1 or 2 or 3 or 4 of its bits.
Is there a way to realize this without using an INOUT port in these inner components?
I have three components A,B,C in a hierarchy of D.
D has a signal X : STD_LOGIC_VECTOR(99 downto 0).
The bits of this vector get modified by all the three components (A,B,C) at different times (Not simultaneously). But each component may change 1 or 2 or 3 or 4 of its bits.
Is there a way to realize this without using an INOUT port in these inner components?