Does TCXO need a buffer ?

Hi everyone,

I am trying to design a reference clock section for my PLL ICs and FPGA. I have a TCXO with 10MHz output ( DOT050F). The problem is it has only 4mA output drive current. Therefore I am planning to use a buffer(5PB1102) and amplifier (GALI-55+). Here is my block schematic.



There are couple of questions I want to ask,

1- TCXO's output characteristic is 15pF, buffer's input capacitance is 5pF , Does a 10pF capacitor parallel to buffer's input result a better matching ?

2- Buffer has a LVCMOS output. Would it be a problem for RF amplifiers like GALI-55+. (I am going to use an AC-coupling capacitor for amplifier's input.)

3- I have researched some schematics for reference clock sections and resistive power dividers are generally used. What is the main reason for this? Is it because it is a cheap way to power divide?

4- Buffer has 2.4V output high voltage at 3.3V Vdd according to the datasheet. Does that mean it has ~17dBm output power :shock: .



Thanks in advance.

A usual (and probably more appropriate) clock distribution scheme would connect multiple LVCMOS buffers to the oscillator output if separate buffered outputs are required.

Don't know what the intended load of the clock distribution network is, but the shown design won't be able to achieve LVCMOS or TTL level.

Regarding point 1, LVCMOS isn't an impedance matched IO standard. 15 pF is a nominal load to achieve the specified rise and fall times etc. You rarely need to add artificial load capacitance to a LVCMOS output.

TCXOs come in various output formats. I've seen PECL,
LVCMOS and "clipped sine wave" myself, recently. If you
are looking for something 50-ohm compatible then LVPECL
might be your pony. But this will be square-ish and have
a lot of upper harmonic content. Seems like this is a radio
type deal and an -un-clipped sine would be your preference.
And/or, a "good enough" filter (which could incorporate an
impedance transformation, if desirable).

Now, if this signal is indeed just the ref clk for an IC PLL,
unloaded HCMOS may be the right answer - no blocking
cap, no termination resistor, you are just bang-banging a
logic level phase detector (perhaps via a few stages of
balanced CMOS inverter gain, which enables use of low
power RF reference signals - but does not preclude better
edge-rate ones). Dig in a bit, there.

+17dBm power presumes the 50-ohm system. Which this
frequency does not need at short-haul interconnect distances.