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FPGA to eMMC clk frequency & adjustable sampling point

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Hello,

eMMC standard JESD84-51

Question is regarding the emmc host clock.
I've read that the host clock operates at fod = 400KHz during identification etc.

From anyone that's dealt with eMMC devices before, what I want to know is
1. When I change the ecsd registers to allow a faster speed, does that mean every subsequent command I send shall operate at the new frequency?
2. When dealing with HS200+ how does one create an adjustable sampling point?

Regards,
Wes
 

Bus sampling tuning concept

Hello all,

What exactly is eMMC standard JESD84-B51 talking about regarding 6.6.5 bus sampling tuning concept?

Previously I raised a question that received no replies, so I'm going to attempt to reword this.

  1. Host controls clock and sends it to the device.
  2. Host requests device to send a tuning pattern by cmd21 on cmd line.
  3. Host captures tuning pattern (sent on data lines) and compares with expected. There shall be 4 or 8 active data lines.
  4. Host finds optimal sampling point for the data lines (I'm confused here)

Last point, am I suppose to increment the sampling point on each line independently

For example dat lines 1, 3, 5, 7 all work on the first clk, whereas other lines are a clk cycle later?

Surely by just monitoring the start bit everything is in sync?

Please send me to some reading materials, for I don't fully understand what the standard is trying to tell me.

Many thanks in advance,
Wes
 
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