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    System Verilog error in modelsim with enum types.

    I have a design which looks like this:

    Code:
    typedef enum { a,b,c d, e} enum_t; 
    
    module test
    		( 
    		output enum_t test_op,
    		input xx,
    		input clk
    		);
    I have a testbench code too where I instantiate module test.

    Code:
    module tb_test();
    
    logic clk,xx;
    enum_t test_op;
    My question is how do I make the enum_t type available for the testbench. I tried defining it in the testbench file, but there is an error during simulation.

    When I dont declare enum_t in the testbench, the error says:

    ** Error: D:/tb_test.sv(11): 'enum_t' is an unknown type.
    Or did you omit the '()' for an instantiation?

    Thanks for any inputs.
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    Re: system verilog error in modelsim with enum types.

    why not put enum_t in a package?



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    Re: system verilog error in modelsim with enum types.

    Quote Originally Posted by TrickyDicky View Post
    why not put enum_t in a package?
    I used the following line for this:
    import enum_types::enum_t;

    Yes. I tried that too. But then I get these types of errors.

    ** Error: D:/test.sv(46): (vlog-2730) Undefined variable: 'c'.

    I have some statements inside the code, where I do,

    test_op = c;

    these lines throw an error.
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    Re: system verilog error in modelsim with enum types.

    Unfortunately, because the enum label identifiers are declared at the same scope level as the enum type, importing just the enum type does not import the enum labels. So you need to import them explicitly,
    import enum_types::enum_t;
    import enum_types::a;
    import enum_types::b;
    import enum_types::c;

    or use a wildcard import
    import enum_types::*;
    Dave Rich
    Senior Verification Consultant
    Mentor Graphics Corporation


    1 members found this post helpful.

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