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Problem with writing a BMM file ROM & RAM memories address space

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sajjad.hussain

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I have generated the following ram and rom from CoreGen:

Code: 
component brom_im
 port (
	clka : IN std_logic;
	addra: IN std_logic_VECTOR(15 DOWNTO 0);
	douta: OUT std_logic_VECTOR(31 DOWNTO 0));
end component;

component bram_dm
 port (
	clka: IN std_logic;
	dina: IN std_logic_VECTOR(31 downto 0);
       addra: IN std_logic_VECTOR(15 downto 0);
	wea: IN std_logic_VECTOR(3 downto 0);
	douta: OUT std_logic_VECTOR(31 downto 0));
end component;
for which i have to write a BMM file. After place and route, I found the following instances names using PlanAhead.

BRAM_instance(bram_dm)
Code: 
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[46].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[53].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[59].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[57].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[44].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[47].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[49].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[62].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[54].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[45].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[43].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[58].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[48].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[60].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[55].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[50].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[52].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[56].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[51].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[63].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[61].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
and
BROM_instance (brom_im):
Code: 
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[50].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_B (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[49].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_B (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[48].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_T (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[48].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_B (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[52].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_T (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[43].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[47].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[51].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_T (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[49].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_T (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[45].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[52].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_B (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[51].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_B (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[46].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[50].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_T (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[44].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)

  1. Based on these primitives how can I write a correct BMM file.
  2. How to use so many bit lanes to access only 32bit wide RAM?
  3. How to use the mix of SINGLE_PRIM36.SP, CASCADED_PRIM36.TDP_T, CASCADED_PRIM36.TDP_B in the bitlanes for the ROM?


Kind Regards
 

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