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Duty cycle detection

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earckens

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I need to detect whether the duty cycle from a circuit drops below a certain value.
Frequency: 2kHz
Amplitude: TTL (0 to 5V)
Step response: an hour or more (it is a very slow system), this is not PWM (duty cycle may change very slowly).
Requirement: detect whether the duty cycle is lower then a adjustable value, most likely less then around 70% (but may also be blow 85% if possible to design a detection for that value).
Hysteresis is required, say about 5 to 10%.

When the duty cycle drops below the preset value a TTL output needs to be triggered. When the duty cycle recovers above the preset value+hysteresis the TTL output needs to be reset. Changes in duty cycle take several hours. However measurements take place once an hour only, during a time adjustable between say 5 seconds and 30 seconds.

A circuit with a flipflop and 2 comparators is my preference. And I want a hardware solution, no software with microcontroller: the circuit has to be universally used without need for software. at a later stage this circuit wil be used in a controller for further processing.
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Hi,

A school project?

TTL levels are >2V / <0.7V ... but they may go up to 5V / 0V. This is a huge source of error., because you can´t rely on the voltage level.

Therefore I recommend to use a CMOS analog SPDT sitch with TTL logic input levels.
NC to to GND
NO to VCC
COM = output

At the output connect a second order low pass filter (simple RCRC) to attenuate ripple and get almost pure DC signal that is proportional to duty cycle.
Use a cutoff frequency of about 25Hz, this results in a ripple of less than 1mV.

This signal is one input of a comparator.
The other input is an adjustable voltage divider (connected to VCC to GND) and a noise filter capacitor to adjust thresold level.

Feedback the comparator output with an appropriate resistor to get the desired hysteresis.

--> one comparator, no flip flop

If you are in any doubt, then you should give a more detailed description with a picture of the signal flow, timing and so on..

Klaus
 

Hi,

A school project?

TTL levels are >2V / <0.7V ... but they may go up to 5V / 0V. This is a huge source of error., because you can´t rely on the voltage level.

Therefore I recommend to use a CMOS analog SPDT sitch with TTL logic input levels.
NC to to GND
NO to VCC
COM = output

At the output connect a second order low pass filter (simple RCRC) to attenuate ripple and get almost pure DC signal that is proportional to duty cycle.
Use a cutoff frequency of about 25Hz, this results in a ripple of less than 1mV.

This signal is one input of a comparator.
The other input is an adjustable voltage divider (connected to VCC to GND) and a noise filter capacitor to adjust thresold level.

Feedback the comparator output with an appropriate resistor to get the desired hysteresis.

--> one comparator, no flip flop

If you are in any doubt, then you should give a more detailed description with a picture of the signal flow, timing and so on..

Klaus

Hi, thank you for this lighting fast feedback.
Signal levels are 0 to 5V
This is for an extension to a project discussed here last year (https://www.edaboard.com/showthread.php?t=353365 where Vitoa used a LTC6905 and AD8307 to generate 100MHz and detect attenuation in a soil sensor. I got that part working although there is lots of work to do to optimize the sensing element design.
As a sideways project I use Audioguru's design in that same page; I use output from pin 11 which is a square wave with load dependent duty cycle. That is what I intend to use as input to a "duty cycle detector": duty cycle drops below an adjustable value (most likely below 80%, but I may tweak that to below 70%) then an output has to be triggered. Duty cycle recovers, then trigger reset.

Here are two scope images, the second is when no trigger is needed (duty cycle <90%), the first when an output needs to be triggered (yellow signals; the blue one is from the probe output, not relevant here). DS1Z_QuickPrint13.jpgDS1Z_QuickPrint12.jpg
 

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