niteshtripathi
Member level 3
Hi all,
I have to do noise simulation of DAC+VCO. So I am doing Pss-Pnoise simulation. For DAC, there is witch capacitor circuit, and input of the DAC are clock signal and trim bit (according to which DAC output voltage get set). According to the DAC output voltage VCO gives a output frequency. I am confused how to do the noise simulation of this schematic and what should be the setting in the Pss-Pnoise simulation. What should be the beat frequeny because there is two clock one for DAC and one generated from VCO.
Any lead will be appreciated. Thanks in advance.
I have to do noise simulation of DAC+VCO. So I am doing Pss-Pnoise simulation. For DAC, there is witch capacitor circuit, and input of the DAC are clock signal and trim bit (according to which DAC output voltage get set). According to the DAC output voltage VCO gives a output frequency. I am confused how to do the noise simulation of this schematic and what should be the setting in the Pss-Pnoise simulation. What should be the beat frequeny because there is two clock one for DAC and one generated from VCO.
Any lead will be appreciated. Thanks in advance.