How much peak-to-peak output ripple voltage of power supply for a digital circuit?

Recently, my research focuses on design power supply (Switching DC-DC converter, LDO) for IoT, extremely-low power and low-voltage applications. Generally, the ripple of power supply follows a rule of thumb (for example 1% of Vout)
(just for an example).

Nowadays, with the state-of-the-art processes. the power supplies for digital circuits such as processor, memory...can be low as 0.5 V (even below this value) . And my question is in that concern, how much acceptable peak-2-peak output voltage ripple of the supply? Is it recommended to follow the rule-of-thumb 1% (for example: with the VDD for digital circuit is 500mV, the acceptable range of VDD is 500mV+/-5mV?)

Thank you!

BRs,

There are several dimensions to this.

Your 1% rule of thumb falls out of error budgeting against
the +/-5% conditions applied to "client" part datasheet
electrical "guarantees". Other claimants include "make"
tolerance (1-2%, initial DC accuracy spec), PSRR,
temperature.

Now there is the very real question of whether 5% is
really all the useful envelope there is, or if maybe +/-10%
is just fine because whatever goes out of spec at 5.1%
or 9.9% just doesn't matter (enough).

If so then you could be fine with 6% ripple.

Ripple transforms to propagation delay and can add timing
uncertainty. Do you know who uses the supply and whether
they are jitter or phase noise sensitive? Modern FPGAs
with high speed serial links and PLLs and such, sure are
and levy pretty tight ripple specs for the special supplies
there.

Lower voltage supplies I think may not be "linear" with
regard to noise tolerance. Both for application sensitivities,
and for less room to accommodate the sum of all "crud",
some of which is constant and some worse, across
generations of technology.

Since you mention IoT, that means radio, means STFU
Mr. Power Supply. You care perhaps about HF PSRR of
the LDO, care about not only conducted ripple but the
higher frequency / edge rate switching conducted and
radiated components.

To great extent, though, ripple voltage is external
component selection and not a lot to be done about
it at the chip design level (DC-DC POL). LDOs bat
cleanup, to greater or lesser success. Filter before
LDO is probably a good play.

Hi,

I don't know about an xx percent ripple specification.
Especially DCDC regulators in burst mode operation will have problems to be within a 1% tolerance.
I rememer on absolute voltage specifications, like "ripple_max = 100mVpp".

A device specified to work on 0.5V (and any other supply voltage value) should give lower and upper limits.
At least this needs to be ensured in any case (load, temperature, aging, noise, ripple..)

Klaus

My sincere thanks to Mr. Dick and Mr. KlauseST,

For clarification, I am doing "digital LDO). The reason I posted this thread is I want to focus on the worse case of VDD with fluctuation mainly caused by load transient condition that the "load" does still properly function. The LDO here is pure "digital LDO" because the analog counterpart can not function under low input voltage condition (especially with VIN < 1V). The problem with digital LDO is that its load transient response is bad as compare to analog LDO. Under load transient conditions, the output voltage might be out of safe margin, I mean large undershoot and overshoot value -> its load does not work properly.

I refereed to several published paper, but still they did not mention about how much the fluctuation in output voltage of the LDO that still powering its (digital) loads & ensure these (digital) loads (loads here can be memory, another digital processing circuits) still works properly.

For example, my design is digital LDO with Vout = 500mV. Also assume that Vout = 500mV+/-(500mV)*a% (a% here can be defined upon applications of LDO).

My final question is, how much a% here. There are very less information on the literature.

Sincerely,



I

Do not look to the present generation of LDOs, look
to the load and its "care-abouts".

Load step response is the toughest challenge in my
experiences with linear regulator design. Digital, in
the best case, can match a good linear loop. But
there's digital and there's digital, some can be too
elaborate and slow to hold up against a harsh load
step dI/dt (and this is the other end of the snake,
the challenge-case that you must hold the deviation
below, during. Much gamesmanship there, and often
unrelated to any load "client"'s needs but more "like
what can we tell marketing, and not eat it at final
test?".

PMOS LDOs do suffer at low VIN, but there are ULDO
(NMOS pass FET, low current higher voltage VAUX
supply for error amp, vref and gate drive with VIN
being a lower, higher current feed),

You might consider "synthetic" or cal-mapped gate
drive if you can sense current directly (along with
other prime factors like VIN and temp). This could
be a good use of digital "smarts", get more in front
of the load step with (say) a "90% right" gate-goes-
to drive that is near real time, and reduce the amount
of effort needed from the feedback loop (thus the
in-the-moment deflection and recovery).

My suggestion remains, that you pick a "client" (I'd
try and make it something geek-sexy, a challenge
but one you think you can solve) and drill into its
supply requirements (spec table conditions, any
app notes regarding supply qualities and issues,
etc.) and pose that as the research goal. There
has to be some class of parts out there (maybe
FPGA, maybe SoC ASIC, maybe a RF module?)
that has enough value to be interesting, enough
provided power quality detail to be used as a
target, and represents some sort of advancement
in the art (of course digital power this-and-that
is quite topical recently and you may have to
thread a path between "already presented" and
"tried and failed"....