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Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 module preload_counter(q, clk, rst, en, load, preload, upd ); input clk,rst,load,upd,en; input [2:0] preload; integer c; output [2:0] q; reg [2:0] q; always @(posedge clk) begin if (rst) q <= 3'b000; else if (load) q <= preload; else if(upd) // else begin q <= q + 1; if( q == 3'b111) begin c = 1'b1; $display("Counter is full count = %b and c = %d",q,c); end end else begin q <= q - 1; if( q == 3'b000) begin c = 1'b0; $display("Counter is empty count = %b and c = %d",q,c); end end end endmodule
How can design shift register with parallel load...................