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Counter Preload by any given values

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sandy2811

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Hello,
How can preload the counter by known value......counter is either synchronous or asynchronous.
if i want to start my counter from 5 then which type of coding is required in verilog....
 

Synchronous logic will be better. I won't give you codes, but hints.

1st do you know how to write code for a simple synchronous up or down counter?

If no, then 1st learn how a simple synchronous counter can be coded with Verilog (Google search will give you 100's of results).

If yes, then you can modify that slightly to allow loading of values from an external port. Keep a single bit input port named such as counter_load_i. Depending on the counter start value to be loaded (for your case it is 5), keep provision for another multi-bit input port through which you can load this value.

Now on the rising edge of your clock, check if your counter_load_i is HIGH (this signal should be high only when you want to load the particular start value, else low). So if it is high, load the value (5) from the external multi-bit input port to an internal register, on the clock rising edge. Next increment/decrement that internal register on the clk rising edge. There...your system is done!
 
Hello,
How can preload the counter by known value......counter is either synchronous or asynchronous.
if i want to start my counter from 5 then which type of coding is required in verilog....

forget asynchronous. make it synchronous. add a reset signal or a load signal that can make the counter value assume e.g. 5
 

use a synchronous counter with reset value 5
 

I have already done this things as you have told, but i want to reset it by using preset or clear logic but i am not getting it perfectly...............
 

Hi,

Show your code.
Then it's more easy to see what (and how) you have done so far...and to give detailled code modifications.

Klaus
 

Hi,

Show your code.
Then it's more easy to see what (and how) you have done so far...and to give detailled code modifications.

Klaus

My code is this



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module preload_counter(q,
                       clk,
                       rst,
                       en,
                       load,
                       preload,
                       upd
                       );
                       
input clk,rst,load,upd,en;
input [2:0] preload;
integer c;
output [2:0] q;
reg [2:0] q;
 
always @(posedge clk)
begin
   if (rst)     
     q <= 3'b000;
 
    else if (load)
        q <= preload;
       else if(upd)
       // else
      begin
         q <= q + 1;
         if( q == 3'b111)
           begin
           c = 1'b1;
           $display("Counter is full count = %b and c = %d",q,c);
           end
         end
       else 
         begin
         q <= q - 1;
         if( q == 3'b000)
           begin
           c = 1'b0;
           $display("Counter is empty count = %b and c = %d",q,c);
           end
       end
end
         
 
endmodule

 
Last edited by a moderator:

I'm sorry what is exactly the problem in this code ?
 

Nothing problem in this code but my idea is to make a counter which is start by a given or known value( i assume 5).
and i want to start counter by this (5) initial value by using preset or clear input.
 

I have already done this things as you have told, but i want to reset it by using preset or clear logic but i am not getting it perfectly...............

In common terminology, a clear input drives a flop to a reset state (this would be similar to what your are doing with the rst signal).
A preset input drives a flip-flop to a set state, and I guess you want the counter value to be 5 when a preset signal is asserted. So just add a sync check for another input signal 'preset' which, if high, will drive q to value 5.

I recommend you to read and understand this:
**broken link removed**
 

Sandy2811, in the code you provided, you need to change the "always @(posedge clk)" to be "always @(posedge rst or posedge clk)" to see the effect of "rst" in simulation
 

Sandy2811, in the code you provided, you need to change the "always @(posedge clk)" to be "always @(posedge rst or posedge clk)" to see the effect of "rst" in simulation

The OP might be modeling a sync reset, we don't know, so he maybe correct!
 

Sandy2811, in the code you provided, you need to change the "always @(posedge clk)" to be "always @(posedge rst or posedge clk)" to see the effect of "rst" in simulation

Thanks but i have design this for synchronous reset.....
 

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