I am using video PHY core IP from xilinx for HDMI transmitter with kintex7 device. It has 3 gigabit transmitters.The phy core has code for TX Phase Alignment to Minimize the TX Lane-to-Lane Skew. But it seems that Tx phase alignment is not completing. I looked inside the phase alignment code and verified in simulation.

1) Phase alignment reset is done
2) RUN phase alignment is asserted(through register configuration)
3) TXPHINIT was asserted for GTX0
3) TXPHINIT_Done was asserted from GTX0
4) TXPHALIGN is asserted for GTX0
5)TXPHALIGN_DONE is asserted from GTX0
6) TXDLYEN is asserted for GTX0 , as a result TXPHALIGN_DONE is deasserted

According to UG476(page 144) GTX0 should assert TXPHALIGN_DONE again. But this step is not happening. I ran the simulation till 2ms.
What can be reason ?

Some info:
The reference clock for GTX= 297MHZ
txoutclock from GTX= 74.25mhz
In video_phy core I changed the 4 counter timings in video_phy_controller_top to speed up the simulation
1)line-1399,1478,1558,1643 *_lock_cnt to 10us(but that will not impact the phase alignment logic)