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17th August 2017, 21:55 #1
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High Level employment of the "imply" operator
Almost all of the 16 possible logic 2variable operations can be exemplified with some kind of what I will call here as a medium/highlevel circuit.
Example:
A XOR gate can be presented with half/fulladders.
ANDs, ORs, NOTs, NANDS, NORs with its several applications (mux, demux, encoders/decoders, etc).
But I couldn´t find an example for the imply operation A > B (or A' + B)
A B A>B
0 0 1
0 1 1
1 0 0
1 1 1
Does anybody know any kind of mediumhigh level example wich uses the imply operator?
Regards

17th August 2017, 21:55

18th August 2017, 00:28 #2
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Re: High Level employment of the "imply" operator
I'm not sure I understand your question; it looks like you already have your answer:
Out=(NOT A) OR B.
This would be an OR gate with B on one input and a NOT gate on the other input; the input to the NOT is A.

18th August 2017, 00:28

18th August 2017, 00:41 #3
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Re: High Level employment of the "imply" operator
Hi berry,
thank you for your reply.
Yes, the imply operator produces the same effect as the A' + B.
What I am looking for is any combinational circuit that regularly employs the "imply as an imply operator".
An example: we usually prefer to express A XOR B instead of A'B + AB'.
Regards

18th August 2017, 00:41

18th August 2017, 07:59 #4
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Re: High Level employment of the "imply" operator
I don't understand the exact problem. You know how to implement the intended logic operation, as a matter of fact an "imply" operator isn't available in most commonly used logic description languages.
Seriously, I don't even see it's purpose.

18th August 2017, 15:16 #5
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18th August 2017, 15:16

18th August 2017, 21:34 #6

18th August 2017, 22:32 #7
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Re: High Level employment of the "imply" operator
I suspect the OP is asking about basic logic circuits that are normally drawn using different types of gates.
For example, xor is used in the conditional invert, fulladder, and parity. xnor for compare equal. "and" for enable.
I'm not familiar of any circuit that performs a basic function that uses this operation. There are certainly complex circuits that have this logic.
I guess CPU pipelines can allow this logic. allow_pipeline_progress = (data_ready implies sink_ready); If data_ready is true and sink_ready is false the pipeline stalls. if data_ready is false the value might not matter.
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