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substitution for loops in design compiler

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moonshine8995

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what should i use instead of loop to be synthesised in dc
i nead a good alternative for the loop which is being used in the below process

Code: 
process (clk)
begin
 for i in 0 to 4999
 LOOP
xn <=(FIR_IN(i));
END LOOP;
 

As shown, the loop is just useless. It only "executes" the last assignment. Explain what you want to achieve and give useful code examples with port and signal definition.
 

FIR_IN is an array with 5000 data. each data in array is 16 bit."xn" is a 16 bit signal.
i want to put each of these 5000 data in "xn" one by one and use "xn" in some functions like sum and mult.because i want to repeat putting data of array in " xn" for 5000 times, i nead a for loop but design compiler give an error.

Code Verilog - [expand]
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FIR_IN : T_2D;
type T_2D is array (4999 downto 0) of std_logic_vector (15 downto 0);
signal Xn : std_logic_vector(15 downto 0);
 

What do you mean exactly with "one by one"? One array value per clock cycle can be output like below
Code VHDL - [expand]
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process (clk)
  variable i: integer;
begin
  if rising_edge(clk) then
    Xn <=FIR_IN(i);
    if i >= 4095 then
      i:=0;
    else
      i:=i+1;
    end if;
  end if;
end process;
 
FvM said:
What do you mean exactly with "one by one"? One array value per clock cycle can be output like below
Click to expand...

I'm pretty sure they mean the want to process each FIR_IN(i) one at a time in sequential fashion. Unfortunately they don't understand pipelined design and that software loops are not the same as VHDL hardware loops.

Loops in VHDL (spatial loop) make replicas of whatever is in the loop, in this case it replicates all assignments to xn until it reaches the last assignment. As VHDL only keeps the last assignment in a process (to the same signal) only xn <= FIR_IN(4999); is kept.

To perform the equivalent software loop (temporal loop) you need to index each array (memory) location with a counter and assign xn in a clocked process like FvM shows. That will take 5000 clock cycles to iterate through all the FIR_IN values. If you attempt to do this temporal loop in VHDL you'll end up with an enormous circuit as it would be completely unrolled into hardware (replication) resulting in a very slow circuit. You can see this when a function with a loop is synthesized.
 
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