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    Compile-time forces (NCSIM and VCS)

    Hi

    I understand that it is possible to force a signal at compile time (with NCSIM at least) so that it will have a constant value every simulation without the need for run-time intervention. However, I can't seem to find any documentation for this on Google.

    Note I would rather not modify the RTL code since this is configuration-dependent and for testing purposes only (not synthesis).

    Is this possible? Ideally I would want to do the same in VCS as well.

    Many thanks

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    Re: Compile-time forces (NCSIM and VCS)

    It should be possible in NCSIM.
    It is possible in VCS.

    Right now I use none of them so this old thread for help - https://www.edaboard.com/thread343499.html

    However, I can't seem to find any documentation for this on Google.
    They are user guides and so are proprietary. Ideally if you are using the tools, you should have access to the help files.
    FPGA enthusiast!



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    Re: Compile-time forces (NCSIM and VCS)

    Quote Originally Posted by ads2017 View Post
    Hi

    I understand that it is possible to force a signal at compile time (with NCSIM at least) so that it will have a constant value every simulation without the need for run-time intervention. However, I can't seem to find any documentation for this on Google.

    Note I would rather not modify the RTL code since this is configuration-dependent and for testing purposes only (not synthesis).

    Is this possible? Ideally I would want to do the same in VCS as well.

    Many thanks
    Verilog has it's own force command, try that instead. It is not simulator dependent.
    Really, I am not Sam.



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    Re: Compile-time forces (NCSIM and VCS)

    Quote Originally Posted by ThisIsNotSam View Post
    Verilog has it's own force command, try that instead. It is not simulator dependent.
    I know but would that not require a whole new SV file just for the forces? I would prefer to specify them on the command line if possible.



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    Re: Compile-time forces (NCSIM and VCS)

    Quote Originally Posted by ads2017 View Post
    I know but would that not require a whole new SV file just for the forces? I would prefer to specify them on the command line if possible.
    on the command line? I am so lost. You said compilation time. Can you clarify what you are trying to do? I suspect you are misusing the force statement to generate stimuli data, which is by definition wrong.
    Really, I am not Sam.



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    Re: Compile-time forces (NCSIM and VCS)

    Quote Originally Posted by ThisIsNotSam View Post
    I suspect you are misusing the force statement to generate stimuli data, which is by definition wrong.
    I'm using a force to compensate for the fact that I've removed parts of the DUT to speed up testing, and I now need to automate this process. Since not instantiating parts of the DUT is inherently a compile-time decision, the compensation should be too.

    So ideally I would like to force signals in various disparate parts of the remaining DUT (in auto-generated submodules which ARE instantiated), and have these forces reside in a single place, preferably as part of the script which generates arguments to the tool. If this is impossible then it will be necessary to create some sideband information for use at runtime, which I would rather not do.



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    Re: Compile-time forces (NCSIM and VCS)

    If you've added code to not instantiate some of the components then you should have also added code for setting those forces when you do not instantiate those parts.



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    Re: Compile-time forces (NCSIM and VCS)

    If you can't make it work with forces, you can replace the modules by a simulation-friendly version of them. Should solve all of your problems.
    Really, I am not Sam.



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    Re: Compile-time forces (NCSIM and VCS)

    Quote Originally Posted by ads-ee View Post
    If you've added code to not instantiate some of the components then you should have also added code for setting those forces when you do not instantiate those parts.
    Code generation scripts prevent this :( And besides, there's no natural location for the forces to reside - I'm forcing configuration registers, not signals coming out of the missing modules. The test input can't be modified.

    Quote Originally Posted by ThisIsNotSam View Post
    If you can't make it work with forces, you can replace the modules by a simulation-friendly version of them. Should solve all of your problems.
    Except that 1) that would prevent the use of emulators, and I wonder whether 2) it could introduce additional bugs which could slow down debugging - better to disable the unused blocks completely.

    Thanks all for your advice, it sounds like it's not possible to do what I had in mind. I'll probably create a new file to contain the SV forces and conditionally include it. (And hope that SV forces work with the emulator...)



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    Re: Compile-time forces (NCSIM and VCS)

    I disagree with 1) and 2).
    Really, I am not Sam.



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