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  1. #1
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    jtag uart speed problem


    i am using JTAG UART fro quartus qsys system to print some values from fpga to nios 2 terminal. the register (32 bit) inside fpga updating at a rate of 10khz,and i am using a clock of 50 mhz to qsys system(to jtag uart). problem is printing every 4th values, in between 3 values are missing .i believe that its the problem of max through put of jtag uart.is there any way i can print all the values, ie did jtag uart can output a 32 bit register at 10khz ?

    i am using cyclone 5 soc kit

    thanks and regards
    Last edited by dipin; 1st August 2017 at 12:40.

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  2. #2
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    Re: jtag uart speed problem

    Assuming the default JTAG clock frequency is 6 MHz like the Xilinx JTAG pod, then to continuously transfer the 32-bits alone with no overhead is 6000000/32 = 187500. Given there is a lot of overhead in the JTAG UART of Xilinx, I'll assume the same is true for the Altera one, I kind of doubt that a factor of 18.75 is enough overhead to transfer the register at 10KHz. If your running the JTAG at even a lower frequency then 6MHz, then the 18.75x overhead is even lower.

    Given that you have a clock domain crossing from the 50 MHz qsys to the JTAG UART will eat into your performance. Along with the conversion from the 32-bit register to a ASCII output over the UART (so it can be displayed) I can easily see you ending up with something more than an order of magnitude worse performance than raw 32-bit serial transfers at a 187.5 KHz rate.

    Xilinx's VIO JTAG update rate is pretty darn slow for status signals and/or the internal ADC temp and voltage sensor. Even at the highest rates it doesn't look like much more than 10's of Hz. JTAG overall is a pretty overhead heavy protocol, so you shouldn't expect much performance. You would be better off not using the JTAG UART and using a UART directly connected to your register logic, which is then connected to some UART-USB dongle on your PC.

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