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    Modelsim - Different istance of the same unit

    hello to all,
    anyone know how to import in modelsim different istance of the same design unit?
    such as, if i want to import in my simulation the same register(named register_N), multiple time, so as at the simulation view under istance i have reg1, reg2 and so on.
    is it possible to do it in modelsim by hand or i must link together with another file in vhdl?

    if i type vsim work.register_N work.register_N modelsim returns an error.
    i think that if i could import with different names and the same design unit i can do what i want. but i cannot know how to do so.

    Thank you.

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  2. #2
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    Re: Modelsim - Different istance of the same unit

    typically all modules need unique names, otherwise the tool doesn't know how to handle them. can't you just rename them externally and avoid relying on modelsim, the worst tool ever created by mankind?
    Really, I am not Sam.



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  3. #3
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    Re: Modelsim - Different istance of the same unit

    so your suggestion is to rename the external file by mean of doing multiple copies of the same design unit and import them to modelsim. is this your idea or i'm misunderstanding?

    i wanted to do it inside modelsim becouse i'd like to export the simulation in order to use modelsim as 'external' simulator so doing all inside modelsim is much better for me since i'm comunicating with it by socket.



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  4. #4
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    Re: Modelsim - Different istance of the same unit

    Do you understand hierarchical design? Do you know anything about designs with multiple instances of other modules/components instantiated in them?

    Seems like you are trying to build up a hierarchical design using modelsim, instead of using modelsim as a simulator of your hierarchical design.

    To simulate a set of registers named reg_1, reg_2, etc based on a single register_N module/component you would instantiate them in another Verilog/VHDL file as instances. eg.
    Code Verilog - [expand]
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    register_N  reg_1 (
      //...
    );
    register_N  reg_2 (
      // ...
    );
    //etc..



  5. #5
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    Re: Modelsim - Different istance of the same unit

    thanks for your reply. It is not a hierarchical design becouse the registers haven't got any correlation between each other.
    What i'm trying to do is to simulate different block in simulink using HDL verifier. My purpose is to build an architecture in simulink and simulate
    it using modelsim, but if i build a hierarchical design as you say i must also create the entity with their port map so that i loose all the advantage of having small block and connect each other in simulink. i do not know if i'm explaining well.

    So I thought that it may be possible to add different "module" (but same design) so that i could import indipendently in simulink and build a complex architecture without really build them in vhdl (or verilog!); but I'm understanding that modelsim doesn't let me do that;

    The problem came from the fact that if i put 2 block in simulink with the same instance (for example i want 2 different input register) the simulation is performed only once and not two time (so the output is the same even if the input are different becouse modelsim perform only 1 request of simulation and assign the output to both the blocks reg). This is why i wanted to istantiate different instance with the same block, so when i import in hdl verifier the block they are different and simulink request 2 different simulation.
    thanks for your help.



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