Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

how to generate prbs in hspice?

Status
Not open for further replies.
D

darush1345

Newbie level 3
Joined
Dec 18, 2016
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
20
how generate prbs in hspice?

hi
how i can have "prbs" in hspice....but no use a lfsr beacuse it does not work!!
can you help me?!
hurry up :)
 

Re: how generate prbs in hspice?

Your implemantation of a LFSR may have failed, but I
am pretty sure that this does not prove it's not viable.

A pwlfile type source can be populated (its state file)
with any series of time/value pairs you like.

A series string of vpulse voltage sources with varying
delays / PWs can emulate a random bit stream.
 

Re: how generate prbs in hspice?

if we can produce a random bit generator in hspice?
please write a code :)
 

Re: how generate prbs in hspice?

pwlfile is probably unhandy for long prbs sequences. Thus a behavioral model of the lfsr feedback circuit may be preferable.

Personally I don't use HSPICE and can't help with an example. I clearly imagine a solution in Pspice or Ltspice, I'm rather sure it exists in HSPICE as well.
 

Re: how generate prbs in hspice?

A question is, just how "random" does this bit stream
need to be? If all you are looking for is a NRZ pattern
that exercises maximum and minimum transition
density, for example, that might be easiest built with
the stack of pulse sources (or, parallel rack of pulsed
currents, terminated by a burden resistor) that make
a few different patterns within the simulation interval.

If HSPICE has a tnoise type capability maybe it has a
noise source that acts in the time domain. Then all you
might need is a clocked comparator behavioral model
to clean it and make logic levels.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top