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writing test bench for modelsim

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wolfheart_2001

wolfheart_2001

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modelsim testbench

hi,

i bought a book on vhdl, the test bench's , the entity_architecture ,packages and packages body are all written in that book, the problem is

when i write the test benches for modelsim many of the examples in the book dont work

for example:

a line like this

clock<= not clock after 25ns;

dont execute in modelsim instead i must type a command to make the clock starts for a period of time

how can i fix that?
 

modelsim testbench example

hi wolfheart,
from the things u have mentioned, i believe that u should write proper and syntax correct testbenches, if ur testbench is correct and still if u get problem

give the code and exact error message displayed by the modelsim, let me see what is the exact problem ?
 

modelsim clock

hi wolfheart,
i found ur code seems to be error free,
i changed and added values of load and enable signals in test bench,
i got values at the output port "output",

ur code is abolutely error free when
simulated with modelsim,
ur try to add
the following values
"wait for 100 ns;

enable <= '1'; " in the process statment of the file shifter_tb.vhd,
and also change the value of "load" in procedure statment of the shift_package.vhd
file and it will definitley work,
 

how write testbench in modelsim

check ur modelsim .. maybe u have chosen the settings to give error if the code is not synthesizable ..
 

how to write testbench in modelsim

if clock is of type std_logic & not initialized u will get an error
as the default for std_logic is 'U' & not 'U' = 'U'
 

writing testbenches verilog modelsim

ur right amraldo,

the simulation works fine now.

thax for all.
 

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