Initializing an input port and then change its value

[mahmood.n]

There is an up/down counter entity where the direction is first set to '1' to count up. Another entity can change the direction if a condition is met. So the test bench looks like

signal c: std_logic := '0'; -- clock
signal r: std_logic := '0'; -- reset
signal d: std_logic := '1'; -- direction
signal cou: integer range 0 to 7; -- count value
...
u0: counter port map( c, r, d, cou ); -- in, in, in, out
u1: reader port map( a, cou, c, d, z ); -- in, in, in, out, out

As you can see the 'd' is initialized to '1'. So, I expect that the counter counts up. However, in the simulation the value of 'd' is U. Well it is correct that assignment is not good because the input 'd' port of the counter receives two wire (one from the initialization and the other from reader).
The architecture of counter is

architecture behav of counter is	
	signal cnt: integer range 0 to 7:= 0;
begin
	process( rst, clk )
	begin
		if (rst = '1') then
			cnt <= 0;
		elsif (clk'event and clk = '1') then
			if dir = '1' then
				cnt <= cnt + 1;
			else
				cnt <= cnt - 1;
			end if;
		end if;
	end process;
	z <= cnt;
end;

Any idea?

[ThisIsNotSam]

why is d an output of the 'reader'? it is conflicting.

if this up/down logic has to be part of the implemented hardware, using a constant to initialise it is a bad idea. make it a flop, add a reset.

[mahmood.n]

why is d an output of the 'reader'? it is conflicting.

Well as I said, upon a condition in reader entity, the direction will be set to down (0).

[TrickyDicky]

If the signal "d" is connected to the ouput of a component, it will not matter what you initialised it to - it will take whatever the reader is driving, which appears to be 'U'.
the initial value is just that - initial. The assignment from the component takes place in the 1st delta of simulation (0ns + 1delta).

[ThisIsNotSam]

Well as I said, upon a condition in reader entity, the direction will be set to down (0).

that's fine. but then it makes no sense to initialise it, ever. that's not RTL.

[mahmood.n]

So, I added a reset input in the reader which set the direction to 1 (up count). That direction output port is connected to the direction input port of the counter. So reader sends either 1 or 0 (down count upon a condition) to the counter.
The reset signal in the test bench is initially 1 and the goes to 0 in the architecture of the testbench. Do you agree with that?

[TrickyDicky]

that would be pretty standard, if you have active high reset.