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  1. #1
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    Does it support to behave like that ?

    Please see the attachment for more detail about the circuit and problem.

    I believe I use 1.6 micro technology (spice model from University).

    Here is the spice model for nmos and pmos transistor :

    simulator lang=spice
    .model nmos nmos
    + level=1 vto=1 kp=16u gamma=1.3 lambda=0.01
    + phi=0.7 pb=0.80 mj=0.5 mjsw=0.3 cgbo=200p cgso=350p cgdo=350p
    + cj=300u cjsw=500p ld=0.8u tox=80n

    .model pmos pmos
    + level=1 vto=-1 kp=8u gamma=0.6 lambda=0.02
    + phi=0.6 pb=0.50 mj=0.5 mjsw=0.25 cgbo=200p cgso=350p cgdo=350p
    + cj=150u cjsw=400p ld=0.8u tox=80n

    I am not sure that does id support to behave like that.
    if I set the width and length to minimum width ( in this technology, it is any value which is above 1.60, therefore I set 1.61.

    In the experiment , I set Vdrain = 2 Volt , and Vgate = 2 Volt , and do parameter analysis(in this case, both width and length from 1.61 to 4 , the width and length always keep in 1) , and plot the id graph

    please comment your thought and theory . Thank you

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  2. #2
    Junior Member level 1
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    Re: Does it support to behave like that ?

    Sorry , guys , I finally understand the MOS transistor model .



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