Lock-in amp. related programmable band-pass/low-pass filter design.

Hello.

I need to realize a couple of programmable filters as part of an lock-in amplifier design, I am sure that I need a programmable low-pass filter for the output of the phase sensitive detector(PSD) and I think that I should make a programmable band-pass filter for filtering the input to the PSD.

But researching this topic have turned out much harder than I had thought it would be, after a few hours of searching for information I am no wiser than I was when I began, if anything I am more confused.

All I seem to find is designs for people who are designing integrated circuits which is impossible for me to make sense out of and so I guess I'll look into active filters and using digital potentiometers to alter the the parameters.

I will read more about active filters but I am somewhat confused as to what I need to achieve.

While reading about lock-in amplifiers I have gotten the impression that a band-pass filter at the input isn't necessarily necessary but that it is a good idea.

The point if the lock-in design I am trying to develop has the ultimate goal of measuring complex impedance but it is also meant to allow me to experiential with that impedance measurement so it has to be able to manage excitation signals up to 1MHz, and below that frequency the adjustability should be as wide as possible.

I am actually not sure what I am asking and why but I cannot get further dealing with this stage and I don't know what I should do/try next in order to make any headway.

Does anyone have any suggestion?

Regards

Re: Lock-in amp. Relatrogrammable band-pass/low-pass filter design.

Hi,

It seems you want to build a universal lock in amplifier circuit. I doubt this is a good idea.

My recommendation: Try to get familiar with it by developing a lock in amplifier for a dedicated application.
This means narrow specifications.

Maybe:
A precise RLC meter with a fixed frequency of 10kHz and a sine shape excitation voltage with fixed amplitude of 1V RMS.
It's more easy to start with.

Later you may try with different frequencies.

Klaus

Re: Lock-in amp. Relatrogrammable band-pass/low-pass filter design.

I'm sure that is solid advice, I will follow that suggestion.

I have a few things I'd like to talk about regarding the realization of a phase sensitive detection(PSD) circuit though, you have previously recommanded a PSD made with a analog switch however while reading online I have found a few similar circuits which I don't really understand the difference of.

Firstly, I have not been able to find a lock-in amplifier(LIA) design or even a description of a LIA that uses a sine-wave as the reference which the also sine-wave excitation signal is multiplied with, which if I have understood the implication correctly would be far superior to a square-wave referenced LIA since if one uses a sine-wave reference then there would not be a lot of other frequencies along side the fundamental that is allowed to pass the PSD.

But is it even possible to multiply two sine-waves in a phase sensitive detection fashion with analog circuits, or is such a scheme only possible in the digital domain?
I am really only curious since I am pretty sure that if such a analog circuit could be designed it is well above my head, though if it is possible I will never be able to stop thinking about it until I have really really tried to make it happen(not concerning to this particular project though).

The largest confusion I have is about the following situation.


First of all, the PSD "action" is controlled by a square-wave so it has two different states or operations, the "simple switch controlled by the reference signal" ether allows the signal to pass or it breaks the signal path, which I think of as ether it multiplies the signal or it disconnects the signal path which is equal to making the signal during this state of the reference period non existent, although some designs connects the switch to ether the signal or to GND which is a much easier situation to think about becasue what would a floating node connected to the low-pass filter result in, I don't know but probably nothing.

But then there seems to be different kinds of op-amp circuits which also uses analog switches but that in both the states of the references period allows the signal to pass through to the low-pass filter, which is often described as ether multiplying the signal with +1 or -1.

But I am not able to figure out if there is a difference between those two scenarios, is there?
That is at least how I understood what i have been looking at.

Re: Lock-in amp. Relatrogrammable band-pass/low-pass filter design.

Hi,

I see one part of the LIA as a switched rectifier.
It is just switching ON/OFF signals. Like a passive switch.
No regulating circuit needed. Therefore one has no problems with phase shift, gain vs frequency, stability...
There are mainly just two introduced errors:
* injected charge. This causes offset, which can be easily compensated/calibrated out.
* additonal series resistance. It just causes a little shift in phase and gain. Usually negligible if you use an appropriate switch.

But if you want to multiply analog signals...this is mathematically more related to "correlation" or "discret fourier transform".
Then - you are correct - the result may be theoretically more informative.
Theoretically, because now you need a regulating circuit, with feedback and all it´s drawbacks.
It is way more difficult to develop a precise circuit.

****

Your PSD confusion.
"breaks the signal path" and "non existent":
I think none of the statements are true....
* Seen from the signal input: the signal is processed continously, if one switch is OPEN, then the other switch is CLOSED, so the signal just flows through another path.
* seen from the output: Either there is the signal, or there is GND. I can´t think of an OPEN or FLOATING signal. (But I don´t have all circuits in mind)

****
multiplying the signal with +1 or -1:
Yes this is the better description than my "controlled rectifier". This is what really happens.

****

I recommend:
* Either start with a simple circuit
* or play around with Excel (or any other method) to simulate the circuit.

Klaus

I've seen phase-sensitive detectors with sinusoidal reference, build with 4-quadrant analog multipliers, but most are actually using square wave reference and "sign-multiplier" detectors. Major drawback is it's sensitivity to odd harmonics of the reference frequency, relevant regarding input signal harmonics and noise reduction.

If the input signal is low-pass filtered with sufficient suppression of 3rd harmonic and above, the method is equivalent to analog multiplier with sine reference.

Phase sensitive detectors utilizing digital signal processing can more easily use an ideal sine reference.

Because third harmonic is the lowest relevant interfering component, you don't necessarily need a continuously tuned low- or band-pass. Low-pass filters with factor 2 frequency step size can basically work.

Additional filters can be useful if the input signal is almost hidden in noise or other signals. This shouldn't be the case with a RLC meter.

Ok so about this simple LIA.

I'll generate the excitation signal with my arbitrary function generator(alternatively a DDS module from ebay using some DDS from ADI) and then get a couple of ether ADG601(1*SPST) or ADG621(2*SPST) for the PSD without any amplifier in front of them. Then to the low-pass filter, I really don't know about this but it sounds as a good idea to me to implement some adjustable low-pass filter in order to be able to find out the effect of different filter cut-offs.

Or would you say that such a circuit is too much as well?

Hi,

You say DDS....does it have a square wave output? Best if two as quadrature..

In my case I always used a CPLD to generate the digitals as well as the analog signal. Therefore I had about jitter free signals with exact timing relation. But I used a fixed frequency, which makes it more simple.

The output LPF really is not critical. Keep it simple.
If you want to build a human readable measurement device...then the update rate should not be more than 3 times per second. And the LPF cutoff frequency does not need to be higher than 10Hz...independent of signal frequency.

For faster output response I used a passive second order RCRC combination.

You don't need an input LPF.

Klaus

I'd like to thank everyone for all advice, I can't say how much a appreciate it.

From the first time I talked about a LIA here on edaboard I have gotten the impression that a CPLD or FPGA would be a great tool for this, and I have recently decided that I will look for a FPGA development board and give it a try and see if I can learn something about it.
I talked with a university professor once which discourage me by saying that that ether you study VHDL and work with that during your career or you don't need to learn anything at all about VHDL/FPGA because the subject requires so wast knowledge about it. So it's really ether only VHDL or no VHDL at all, I had no more chance to talk to him about this so I don't really know what he meant to tell me.

Or am I wrong to put FPGA and CPDL in sort of the same genre of ICs/type of applications?

If the following is true I will open a peerage thread discussing PLLs, but I have been reading a fair amount about phase locked loops and it is still unclear to me if a PLL may be used to introduce a 90deg phase shift to the signal while it is required to lock over a adjustable range between 100Hz - 1MHz?

I have read something about PLLs having a minimum frequency which might cause problems if I want to lock it to 10Hz - 1MHz but the IC cd4046 I think it is looks appropriate for such a range.

This is thoughts besides those about exploring a rudementary LIA which I am in the process of doing.