Simulation in modelsim.... Multiple Drivers.......

Hi all...
i have been trying to simulate some code in which there is a data bus
that is declared to be of INOUT type. I have simulated my VHDL code and
for both read and write operations it works fine, also the data bus
gets tri-stated (Z) when not in use.
Now this simulation was done by directly putting the values of signals
in the ModelSim environment. Then I thought to write a testbench to
simulate the same. In this case when I write some data on the databus
it does not get tri-stated when not in use. So i tried to debug the
problem and found that since in my testbench I am forcing some value on
the bus say '3B' and also in code i force 'Z' when not in use, then
STD_LOGIC being a resolved type resolves the value and gives '3B' since
'Z' has got least priority.
Why it worked directly on ModelSim environment was bcoz i was
"Depositing" the value on bus and not "Freezing" it. If i freeze the
value there then in that case also i cud not make the bus tri-stated.


So i would like to know how in our testbench we can write code such
that i can see all the correct results. I think in practice this will
work fine but it's better if in simulation also we can see the desired
results. Hope somebody can help. Thanx a lot [/color]

If i understnd your problem, then it is like U want your DataBus to be tri-stated even in the case of Test Bench. You have well analysed the problem and have yourself answered it. When you "Deposit" in your ModelSim environment and no such case in Test Bench. So, ideally you should put Data on DataBus for that duration, when it is used only and after that 'Z' it; like "3B" after 250 ns "Z" after 350 ns;
I am trying to reproduce the problem but that should be the ideal way. Plz revert back with your ways.

Hi SPARC.....
Yes whatever you told is right. Actually we can model the data bus in that manner by specifying 'Z' after some delay and again enabling. The reading is also proper from the data bus. But my doubt was if we can put some syntax that can perform the function of what 'Deposit' does in force command in ModelSim, so that we dont hav to model data bus also everytime we provide the data as that work could have been done by our program itself.
I searched some PDF's on net n found that there may b a provision for this type of testbench writing in the new version of VHDL i.e. 200X. But if you hav any other alternative then do reply. Anyway thanx a lot for the help.