Offline voltage spike gernerator to test LED driver is failing....why?

Hello,
We have some 230VAC Offline LED driver IC’s which have a Vdd pin which connects directly to the Post mains rectifier DC Bus. The Vdd pin has an absolute maximum 450V rating.
Therefore, we have been exposing them to voltage spikes with our offline spike generator, so as to see if the LED driver holds up to it. This simply switches on at the mains peak and an LC circuit rings up to twice mains peak and zaps the LED driver under test. (as attached).

The first two units I tested never lit up, and the FETs of the spike generator were killed (short from Drain to Source). Do you think a short term surge current (due to the led driver ic being killed) killed the FETs?.....or do you think our setup, with a high side supply provided by a mains adapter with a Y capacitor between its pri and sec which could be transmitting occasional surge pulses to our high side fet switching circuitry, is responsible?
Only one of the back to back FETs was killed. Do you think we need to use IGBTs in their place?

SIHP24N65E FET datasheet (FETs used in back-to-back-FET switch)
https://www.vishay.com/docs/91475/sihp24n65e.pdf

I haven't tried any simulation but at first glance I can't see what D19 and D20 do as they parallel the existing internal diode in the MOSFETs. Likewise, why R16 and R17 when one would do, they are in parallel and have no special power dissipation needs.

The CNY17 is optimized for 10mA LED current but you only run it at around 3mA assuming it is powered from the 5V from your PIC project.

Speaking of that, if you are using a transformer supply for the PIC and monitoring it's secondary for zero crossing, are you taking into account the phase shift when you look for peak voltage?

Brian.

Speaking of that, if you are using a transformer supply for the PIC and monitoring it's secondary for zero crossing, are you taking into account the phase shift when you look for peak voltage?

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Thanks, the zero crossing detector comes directly from the mains.....its an EL827 dual opto, with the diodes in reverse parallel, and a series resistor, between live and neutral. (as youll know, the two transistors of the opto are connected to a pullup, also connectd to the micro.)

Attached please find the LTspice simulation of the spike generator.

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What’s worrying us is the failure of the FETs……if this is due to the surge current drawn by a dying “product under test”, then we are happy, because then we only have to use beefy IGBTs as a replacement…………but what would cause more concern, is if the high-side circuitry surrounding the FETs is coupling in some noise or pulses which is killing the FETs.
I think just mentally, the sight of that high-side circuitry sitting there precariously on the mains live just looks odd to me, and I am wondering if there is some failure mode associated with it?

We would have used a contactor to switch the mains on at mains peak, but the problem is that they bounce and that would obliterate the narrow voltage spike pulses that we can get with a non-bouncing FET switch. I do wonder if there is such thing as a cheap mains contactor or mains relay that doesn’t bounce, or at least not for more than a few microseconds?

I'm not clear on your description of the failure. Are the FETs in the spike generator only being damaged, or are the DUTs also failing? Is the driver IC for the spike generator failing?

Ideally if you want to test against line surges, you should make it so the surges happen during normal operation. In your case, the surge comes with along with the normal inrush current, which will put more stress both on the spike generator and the DUT. Take a look at this document for ideas on how to properly inject shaped pulses during normal operation.

I'm not clear on your description of the failure. Are the FETs in the spike generator only being damaged, or are the DUTs also failing? Is the driver IC for the spike generator failing?

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Thanks, DUT's are also being damaged.
The driver IC of the spike gen is not failing.

......we have a way to do transients in normal running operation.....it involves two of the "switchs" shown in top post.....we would run it through the first switch to start off....then switch that off for 100us, and in that time we would switch in and out the LC resonantor via the other switch.....it would have a diode leading from the LC to the product so that it did not interfere during the initial normal running.

Thanks, i will read your doc.

Please find sim in ltspice of our "normal running spike generator"

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Thanks for your doc Mtwieg, it is very good. As far as implementation is concerned though, we will have to stick with the circuits we have here as i couldnt see how to implement the ones in the doc.
Does anyone see problems as discussed with our high side FET drive circuitry?

treez said:

Thanks, DUT's are also being damaged.
The driver IC of the spike gen is not failing.

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Then the simple explanation is that the DUT is failing first, which then causes the surge generator to fail by overload. The devices in the surge generator should be made with components much more durable than the DUT, or contain some sort of fast limiting circuitry. But you should confirm that the initial failure is in the DUT first.