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Gate Level Simulation in Cadence AMS

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sinaa92

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Hello everyone.
Im working on a mixed signal project. I have simulated my RTL level of digital section with analog parts in Cadence AMS design. After synthesizing the RTL code I want to repeat my mixed mode simulation but I cant. I dont know how to add sdf file and technology file for simulation
does anyone has experience in mixed mode simulation with gate level verilog??
 

You don't use SDF files in the 'analog simulators', you use it in the 'digital simulators' like ncsim. Make ncsim the top simulator and integrate your analog needs.
 

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