msdarvishi
Full Member level 4
Dear all,
I am using Vivado 2017.1.targeting a Zynq 7000 clg484 FPGA and I did synthesis and implementation of my design successfully without any warning or error. I would like to perform a post-route timing simulation but I received the following error message
Even, after changing the library to xil_defaultlib for the design files and testbench, the problem still exists, and gives the following error message:
We know that the work path does not exist anymore in Vivado, so based on my search in forums, the solution is to change the library to xil_defaultlib ! that does not solve the problem even for the latest version of Vivado 2017.1 !!!
Also, by looking at the design's path :
D:\Xilinx\my_design\my_design.sim\sim_1\impl\timing\xsim.dir
we will see NO work directory or file !!!!! It seems too weird. Do you believe that this problem did not resolved by development team in Vivado even until Vivado 2017.1 version??? If so, the Vivado is NOT able to perform a post-route timing simulation !!!!!! It is a big bug there though !!!
Kind replied and helps are mostly appreciated !
Thanks and Regards,
I am using Vivado 2017.1.targeting a Zynq 7000 clg484 FPGA and I did synthesis and implementation of my design successfully without any warning or error. I would like to perform a post-route timing simulation but I received the following error message
Even, after changing the library to xil_defaultlib for the design files and testbench, the problem still exists, and gives the following error message:
ERROR: [XSIM 43-3225] Cannot find design unit work.ps in library work located at xsim.dir/work.
We know that the work path does not exist anymore in Vivado, so based on my search in forums, the solution is to change the library to xil_defaultlib ! that does not solve the problem even for the latest version of Vivado 2017.1 !!!
Also, by looking at the design's path :
D:\Xilinx\my_design\my_design.sim\sim_1\impl\timing\xsim.dir
we will see NO work directory or file !!!!! It seems too weird. Do you believe that this problem did not resolved by development team in Vivado even until Vivado 2017.1 version??? If so, the Vivado is NOT able to perform a post-route timing simulation !!!!!! It is a big bug there though !!!
Kind replied and helps are mostly appreciated !
Thanks and Regards,