shanmei
Advanced Member level 1
"in" is the signal, the start and end point is unknown.
clk is the clock signal from outside of the chip, and its phase can't be changed.
I need to use one high-frequency and one low-frequency clock to count the signal "in".
in case 1, t2 is the time counted by the low-frequency clock. t1 and t3 are counted by high-frequency signal clock.
in=t1+t2-t3.
If I can synchronize the "in" signal and the low-frequency clock, as in case 2, t4 is the time counted by the low-frequency clock. t5 is counted by high-frequency signal, then the time of "in" is:
in=t4-t5.
It is conventient for me in case 2, since there is only one time interval counted by the high frequency clock.
How can I delay the "in" signal to synchronize the clk rise edge?
I want to achive it without complex logic, do not use pll. Is there a way to deal with it? Thanks.
clk is the clock signal from outside of the chip, and its phase can't be changed.
I need to use one high-frequency and one low-frequency clock to count the signal "in".
in case 1, t2 is the time counted by the low-frequency clock. t1 and t3 are counted by high-frequency signal clock.
in=t1+t2-t3.
If I can synchronize the "in" signal and the low-frequency clock, as in case 2, t4 is the time counted by the low-frequency clock. t5 is counted by high-frequency signal, then the time of "in" is:
in=t4-t5.
It is conventient for me in case 2, since there is only one time interval counted by the high frequency clock.
How can I delay the "in" signal to synchronize the clk rise edge?
I want to achive it without complex logic, do not use pll. Is there a way to deal with it? Thanks.