# how to synchronize the signal and the external clock

1. ## how to synchronize the signal and the external clock

"in" is the signal, the start and end point is unknown.
clk is the clock signal from outside of the chip, and its phase can't be changed.
I need to use one high-frequency and one low-frequency clock to count the signal "in". in case 1, t2 is the time counted by the low-frequency clock. t1 and t3 are counted by high-frequency signal clock.
in=t1+t2-t3.

If I can synchronize the "in" signal and the low-frequency clock, as in case 2, t4 is the time counted by the low-frequency clock. t5 is counted by high-frequency signal, then the time of "in" is:
in=t4-t5.

It is conventient for me in case 2, since there is only one time interval counted by the high frequency clock.
How can I delay the "in" signal to synchronize the clk rise edge?

I want to achive it without complex logic, do not use pll. Is there a way to deal with it? Thanks. •

2. ## Re: how to synchronize the signal and the external clock

Not quite clear what you want, but perhaps a D-Flipflop with the D connected to the "in" signal and its CLK provided by the high frequency clock would do what you need.

1 members found this post helpful. 3. ## Re: how to synchronize the signal and the external clock

Basically, you need to synchronize both the rising and falling edges. The way I would approach this, and I'm sure there are others, is to use a single high-speed clock whose frequency is determined by your accuracy requirements, and sample the input with that. Maybe you need a synchronizer, maybe not (if you don't care about metastability). As proposed by my esteemed colleague Crutschow, use a dff; use the Q output to enable a counter which is clocked by the high speed clock. There's no need to fart around with two different clocks.

1 members found this post helpful. •

4. ## Re: how to synchronize the signal and the external clock

Thanks.

Clk is the low-frequency clock, and another high-frequency signal is used to count the residue signal (T1 and T3 in case1).

The reason to use two frequency signals is to reduce the power. If a long time "in" signal counted only by a high-frequency clock, then it will consume too much power. 5. ## Re: how to synchronize the signal and the external clock Originally Posted by shanmei Thanks.

Clk is the low-frequency clock, and another high-frequency signal is used to count the residue signal (T1 and T3 in case1).

The reason to use two frequency signals is to reduce the power. If a long time "in" signal counted only by a high-frequency clock, then it will consume too much power.
Too much power? How much is "too much"? How much power will the additional complexity of the two-clock circuitry consume? What kind of application is this?

1 members found this post helpful. •

6. ## Re: how to synchronize the signal and the external clock

First of all, define: "long time". Is it an hour, a day, a year?

Then define the "residue", is it a second, a millisecond, a nanosecond?

Without specific parameter values we are only wildly speculating.

1 members found this post helpful. 7. ## Re: how to synchronize the signal and the external clock

The maxim total time is around 100uS with the coarse clock of 1MHz, and the fine clock frequency is 1GHz. --[[ ]]--