dzafar
Member level 4
Hello there,
I am studying pipelining and came across the following example. In the image below the top circuit shows that the critical path is 5ns (assuming 1ns gate delay). The bottom circuit shows that they "pipelined" the circuit.
I have a lot of questions!
1. Why divide it into 2ns and 3ns? Why not 1 and 4?
2. Why put 3 flip flops? Why not just 1 in the actual critical path?
3. How do we know if we are supposed to use pipelining?
Also,
What does point 2 of above image mean ... "We can sometimes have multiple data items “in flight” at once"?
Also, in the image below, don't we also get an overhead of T_hold?
Thanks in advance
I am studying pipelining and came across the following example. In the image below the top circuit shows that the critical path is 5ns (assuming 1ns gate delay). The bottom circuit shows that they "pipelined" the circuit.
I have a lot of questions!
1. Why divide it into 2ns and 3ns? Why not 1 and 4?
2. Why put 3 flip flops? Why not just 1 in the actual critical path?
3. How do we know if we are supposed to use pipelining?
Also,
What does point 2 of above image mean ... "We can sometimes have multiple data items “in flight” at once"?
Also, in the image below, don't we also get an overhead of T_hold?
Thanks in advance
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