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Piplelining for critical path delay

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dzafar

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Hello there,

I am studying pipelining and came across the following example. In the image below the top circuit shows that the critical path is 5ns (assuming 1ns gate delay). The bottom circuit shows that they "pipelined" the circuit.

Untitled.png

I have a lot of questions!
1. Why divide it into 2ns and 3ns? Why not 1 and 4?
2. Why put 3 flip flops? Why not just 1 in the actual critical path?
3. How do we know if we are supposed to use pipelining?

Also,

Untitled.png

What does point 2 of above image mean ... "We can sometimes have multiple data items “in flight” at once"?

Also, in the image below, don't we also get an overhead of T_hold?

Untitled.png


Thanks in advance :)
 
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1. Why divide it into 2ns and 3ns? Why not 1 and 4?

You try to divide the critical path into M portions where each of these M portions have almost the same delay. In pipelining, you need to allow the combinational circuit between two successive flip-flops to operate and calculate the result, then, with clock edge, the calculated data is stored in the flip-flop and now you can use the same combinational circuit for the next set of data. Since all of the flip-flops operate with the same clock, all of the combinational circuits have the same time to operate. If one of these combinational sections is faster than the others it will remain idle for some time (it has calculated the result of previous data but you are not giving new data to it), and if it is slower than other portions, it will not have enough time to calculate the result.

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2. Why put 3 flip flops? Why not just 1 in the actual critical path?

You have three outputs from the first section of your circuit, you need three memory units (flip-flops) to store that data.
 

1. It would give a better balance. at 1/4 ns split may mean the 4ns region then fails timing.
2. This assumes that the 3 inputs are parrallel. If you only split the citical path, the other signals would no longer be aligned, and you change the behaviour of the circuit.
3. Because you failed timing, or you suspect it will be a difficult area to route.

4. see 2.
5. No - hold it the minimum time that a signal MUST be stable before it is read into the circuit. Therefore if you violate setup time, you're also violating the hold time.
 

1.) 3ns allows 333MHz. 4ns allows 250MHz. 333MHz > 250MHz.
2.) already answered. Some developers will do what you describe. It makes the design much harder to understand when the interfaces have signals with different delays.
3.) This comes down to experience. Many developers will pipeline whenever possible. For FPGAs, where the registers already exist, this is effective.
 

5. No - hold it the minimum time that a signal MUST be stable before it is read into the circuit. Therefore if you violate setup time, you're also violating the hold time.

What? Hold and setup are checked at different times. This is absolutely not true.
 

What? Hold and setup are checked at different times. This is absolutely not true.

Ok, true, but if you failed setup, you're giving the tool less chance of meeting hold as you're eating into the hold time.
 

I understand what you are saying. That said, if a critical path has a setup error I don't think that the the tools will also flag it for a hold error. At least, under sane cases where the requirement is > setup+hold.

Specifically, I think the tools only report setup errors for paths that have too much delay relative to clock and hold errors for paths that have too little delay relative to clock.

That said, I haven't used every tool. I would be upset if a tool reported a long path as a hold error though.
 

To be honest, in FPGAs, you're very unlikely to see a hold error at all, as getting too short a path is near impossible. You're likely to only ever worry about setup timing, and recovery and hold for reset paths.
 

To be honest, in FPGAs, you're very unlikely to see a hold error at all, as getting too short a path is near impossible. You're likely to only ever worry about setup timing, and recovery and hold for reset paths.

You can see hold error problems when there is really bad skew problems between source destination clocks. I've seen this happen where a design was using another buffered clock for the destination (same frequency, synchronous), the problem was you couldn't add enough delay to the path (for the fast corner) to fix hold without violating the setup time on the same path for the slow corner. The fix involved fixing the screwed up clocking scheme (some people never go through the warnings).
 

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