Evaluation Kit Xilinx Zc702 with two Ethenet PHY (SoC Zynq)...

Hello folks!

I am working in a new design based on the Xilinx evaluation kit Zc702. I wanna preserve the most of the parts of the evaluation board but I need to attach to independent Ethernet PHY to the Processor Part. I ahve searching in internet and I did not found any info about it. And after reading the user manual of the evaluation kit (ug850-Zc702-eval-bd) I have a question at this point:

"On power-up, or on reset, the PHY is configured to operate in RGMII mode with PHY address 0b00111 using the settings shown in Table 1-13. These settings can be overwritten using software commands passed over the MDIO interface"



The question is: Which should be the configuration of the second Ethernet PHY to reach a proper individual working of both ethernet interfaces? What changes should I do in the schematics??

Thanks in advance.

I think the table shows the default settings for the Marvell Alaska PHY device (88E1116R). If I am not mistaken the eval on-board PHY should support by default gigabit mode with auto-nego enabled.

The question is: Which should be the configuration of the second Ethernet PHY to reach a proper individual working of both ethernet interfaces? What changes should I do in the schematics??

Click to expand...

Consult the data sheet of your 2nd PHY to see the schematics that would enable auto-negotiation.

Thanks for the quick answer...I am going to use the same PHY for the second Ethernet interface.... Should o think that it supports auto negotiation. But what about the address?

See the table given above pertains to the connections of the PHY 88E1116R as it is in the Zc702.
If you want your 2nd PHY to have exactly the same schematics then use the same table.

But I would recommend to get an NDA from Marvell and look into the Alaska PHY device (88E1116R) datasheet. It is a must, you want to design your own schematics.

PHY address 0b00111 (dec 7) is default address for all Marvell PHYs in Xilinx dev boards. You may want to keep the same or change it. Basically this PHYAD is the address of the PHY which the TEMAC core refers to when it wants to READ/WRITE the contents of PHY registers.