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    Verilog Hardware description language

    Hi,

    Design a two stage pipeline 16 bits adder with verilog code, assume you can use
    the 8 bit adder macro module .The input and output signals are defined as:
    input [15:0] a, b;
    input clk, cin, rst;
    (rst is asynchronous reset signal, only reset at neg
    ative edge)
    output [16:0] sum;
    output: cout

    Can anyone provide me the verilog code for this. Please it's very urgent

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    Re: Verilog Hardware description language

    Wrong forum.
    Try posting here:

    https://www.edaboard.com/forum32.html



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    Re: Verilog Hardware description language

    Nobody is going to do your work for you. We will help out with specific question, but we won't write code for you.

    I suggest you do one of the following
    a) tell your boss you need help
    b) study more
    c) hire a consultant to do the job
    d) post the same question on stackexchange and have the notoriety of a post with a -100.



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    Re: Verilog Hardware description language

    The pipelined addition and the pipelined accumulator have the same structure.

    The upper 8 bits have a reg - adder - reg structure.
    The lower 8 bits have a adder - reg - reg structure.

    The carryout of the lower 8b section is registered and this is used as the carry in for the upper 8 bits.



    It is lesser known that the same method applies to accumulators, allowing accumulators to be pipelined.



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    Re: Verilog Hardware description language

    Hi VGoodtimes...Thanks a lot for your reply

    This is what I have done so far....I am new to this but I am still trying...If possible please help...


    Code Verilog - [expand]
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    module sixteen_adder(   
       output co,
       output [15:0] s,
       input [15:0] a,b,
       input cin);
     
       wire [1:0] carry, p, g;
       wire pa, ge;
     
       wire c1,c2;
     
       adder8 add1 (.co(c1),.s(s[7:0]),.pa(p[0]),.ge(g[0]),.a(a[7:0]),.b(b[7:0]),.cin(cin));
       adder8 add2 (.co(c2),.s(s[15:8]),.pa(p[1]),.ge(g[1]),.a(a[15:8]),.b(b[15:8]),.cin(carry[0]));
       
       
                                                                                                               
        code(.pa(pa),.ge(ge),.cout(carry),.p(p),.g(g),.cin(cin));
     
       assign co = carry[1];
    endmodule
     
    TEST BENCH
     
    module sixteenbit;
    reg[15:0]a;
    reg[15:0]b;
    reg cin;
    wire[15:0]s;
    wire co;
    endmodule
    Last edited by bassa; 4th April 2017 at 04:02. Reason: add code tag



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