VCO output swing (2 times of VDD?)

Dear guys:

I am using 1.2V supply to simulated a VCO under 45nm CMOS. The topology is cross-coupled with a PMOS current source. The DC current flowing through current source is 2.4mA, and a 1nH PDK inductor is used (Q>20). The operation frequency is 30GHz.

When the VCO is loaded by a simple differential buffer, the output swing of each VCO branch is 2V, almost 2 times of VDD, and the differential output swing is 4V. So is it reasonable? Any breakdown problem for the loading buffer?

Thanks for attention!

The swings are expected if the VCO is operated in the voltage limited regime. To protect the VCO from breakdown, sometimes reverse bias diodes are used to protect the device from these stress conditions.

Thanks deba. As you mentioned, a reversed bias diodes are needed to prevent breakdown, however this may not be acceptable in my project as the frequency is 30GHz and beyond. By the way, I am using deep N well RF NMOS, so do you mean that I can change the bulk or DNW voltage to release the stress? In 40nm CMOS, which terminal is easier to breakdown, think film gate oxide or drain-to-body diode?

Thanks in advance.

NovelPanda said:

... which terminal is easier to breakdown, think film gate oxide or drain-to-body diode?

Click to expand...

Thin gate oxide of course; a drain-to-body diode can't break down, it could just be forward biased.

D-B diodes certainly can break down. But usually D-S
punchthrough comes first. And reliability will be
compromised well before either one, device drifts
(VT match, elevated "off" leakage, oxide wearout).
Presumably the VCO core is NMOS and a NMOS that
can barely take VDD-VS, may break down, enter
punchthrough or impact ionization at (2*VDD)-VS.

A LC VCO, by its L, can swing output above VDD.
Depending on the quality of your MOSFET model,
the D-B diode may or may not show its true operation.
Likewise D-S nonidealities. Modeling dudes can be lazy
and be whipped to turn out a normal-operation model
so quick that abnormal features get zero attention.
This is very normal organizational behavior, alas.
And it is why every circuit designer ought to try to
understand device design and device reliability.

Give a simple DC sweep simulation a try and see if it
looks realistic based on your understanding of device
parasitics and the circuit involving the true body
connection.

Thanks erikl and freebird. In our previous tapeouts we did not find breakdown issue under nominal voltage, but sometimes we may need to increase the VDD. Perhaps the most possible device suffering from breakdown issue is varactor, which is recommended to be a IO version (2.5V) rather than core one (1.2V).