+ Post New Thread
Results 1 to 3 of 3
  1. #1
    Member level 1
    Points: 1,114, Level: 7

    Join Date
    Aug 2013
    Posts
    33
    Helped
    0 / 0
    Points
    1,114
    Level
    7

    An optimal True Random Number Generator for FPGAs?

    Hi All,

    I want to generate a true random number in Actel ProAsic3 FPGA development board which operates at 48 MHz. I tried to implement it using ring oscillators (RO) and used the system clock i.e. 48 MHz as sampling frequency. As the sampling period is around 48 MHz => 21 ns, the RO period should at least be double the sampling frequency, i.e. 42 ns, means that my RO has approximately 41-45 inverter (NOT gates). Hence, the resource utilization of my target design will be increased by 45 additional core cells (approximately for RO + D flipflop), but i may only have hardly 10-15 additional core cells left unused in the device.

    I need any suggestion to implement the optimized version of true random number generator as per my system clock frequency i.e. 48 MHz.

    Thank you in advance.

    •   AltAdvertisment

        
       

  2. #2
    Advanced Member level 4
    Points: 8,007, Level: 21
    Achievements:
    7 years registered Created Blog entry
    dpaul's Avatar
    Join Date
    Jan 2008
    Location
    Germay
    Posts
    1,191
    Helped
    257 / 257
    Points
    8,007
    Level
    21
    Blog Entries
    1

    Re: An optimal True Random Number Generator for FPGAs?

    Have you considered the scenario of lowering the 48 MHz sampling frequency?
    Let the FPGA input be 48MHz but use a PLL inside to obtain a lower freq which you might want to use as sampling frequency.
    FPGA enthusiast!



    •   AltAdvertisment

        
       

  3. #3
    Member level 1
    Points: 1,114, Level: 7

    Join Date
    Aug 2013
    Posts
    33
    Helped
    0 / 0
    Points
    1,114
    Level
    7

    Re: An optimal True Random Number Generator for FPGAs?

    I think this will not work out. Say, if the sampling frequency is lowered to 20 MHz i.e. 50 ns, then RO period should at least be double the sampling period, i.e. 100 ns. This method will ultimately increases the TRNG size, but not optimize it.



--[[ ]]--