verilog code to automatically activate the outputs of demultiplexer

• You used a for loop to generate slct.
• The select shouldn't be generated in your demux code in the first place, it is an input to this module.
• You've defined slct as an integer but are doing a compare to a single bit (perhaps you should learn VHDL it won't allow bad stuff like this).
• You are missing slct from your sensitivity list of the always, and why aren't you using always @* to avoid this missing stuff in the sensitivity list?
• Not using the Verilog 2001 module port (C-like) declarations. I haven't seen a simulator/synthesis tool that can't handle that for many years now. i.e. it's supported, there is no need to use the antiquated and repetitive syntax.

Code Verilog - [expand]
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module trrrrr (
  input      slct,
  input      fis,
  output reg f0,
  output reg f1
);
 
  // using if
  always @* begin
    if (slct == 1'b0)  {f1, f0} <= {1'b0, fis};
    else               {f1, f0} <= {fis, 1'b0};
  end
 
  // using case
  always @* begin
    case (slct)
      1'b0 : {f1, f0} <= {1'b0, fis};
      1'b1 : {f1, f0} <= {fis, 1'b0};
    endcase
  end
 
endmodule

ecasha said:

Hey,I have written verilog code for the 1:2 demux,I want to activate the outputs one after the other without giving select inputs manually.When I run it ,its showing the only f2 output.I want to see both outputs i.e first when select =0 and select=1 one after the other.How to rectify it?

Code:

module trrrrr(FIS,f0,f1);
input FIS;
wire FIS;
output f0,f1;
reg f0,f1;
integer slct=0;
 always @(FIS) begin
 for(slct=0;slct <= 1'b1;slct = slct+1)begin
if (slct== 1'b0)begin
	  f0=FIS;
     f1=0; 
		end
   else begin
    f0=0;
    f1=FIS;
    end
end
end
endmodule

View attachment 137382
Above is the output what I am getting.

Click to expand...