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Multiple VHDL source files simulation with Active-HDL

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mahmood.n

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I am using Active-HDL to write VHDL codes. I am able to write ans simulate one file codes but when it comes to multiple source files and components, the simulation doesn't work! It seems that there is a problem finding components in other source files. Please see the attached picture.


As you can see in the left pane, the test bench is selected as the top level. Any idea for that? the code is pretty simple and should work! ac.jpg
 

All related sources have to be compiled to the library work.
 

Can you explain how? Because, I wrote the same code with ISE and it was fine. FYI, in Active-HDL I compile all files and actually it detects the file order.

Code: 
acom -dbg -work fulladder3 -2002  $dsn/src/ha.vhd $dsn/src/fa.vhd $dsn/src/tb.vhd
# Compile...
# File: c:\My_Designs\fulladder3\fulladder3\src\ha.vhd
# Compile Entity "ha"
# Compile Architecture "x" of Entity "ha"
# File: c:\My_Designs\fulladder3\fulladder3\src\fa.vhd
# Compile Entity "fa"
# Compile Architecture "y" of Entity "fa"
# File: c:\My_Designs\fulladder3\fulladder3\src\tb.vhd
# Compile Entity "tb"
# Compile Architecture "z" of Entity "tb"
# Compile success 0 Errors 0 Warnings  Analysis time :  0.1 [s]
 

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