Calibre LVS errors for a design generated in Encounter

Hello all,

I made a design in SoC Encounter using NangateOpenCellLibrary 45nm. The layout had zero geometry and connectivity violations. I then needed to go to Calibre for LVS and PEX in order to do post-layout simulations, so I did the following in Encounter:

1) Design > Save > GDS/OASIS, then I provided the map file and merged library gds file that came with PDK "NangateOpenCellLibrary.gds" and didn't select "Uniquify cell names"....then finally hit Ok.

2)Design > Save > Netlist, and I selected the two options in the window and hit Ok.

Then for Calibre part:

1) I run "v2lvs" command to generate spice netlist for LVS

2) I then run LVS using Calibre -gui

In LVS transcript window, I get tons of these two warnings:

Open circuit - Same name on different nets:

Top level port name "KEXP0/n2089" at location (3.515,165.69) on net 2 not valid for netlisting; net id used instead.

(I think the above warning is the reason of the errors)

and in the LVS report I get these:

Error: Different numbers of ports (see below).
Error: Different numbers of nets (see below).
Error: Different numbers of instances (see below).
Error: Connectivity errors.
Error: Property errors.
Warning: Unbalanced smashed mosfets were matched.
Warning: Ambiguity points were found and resolved arbitrarily.
Warning: LVS property resolution maximum exceeded.


NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------

Layout Source Component Type

------ ------ -------------

Ports: 12065 35 *

Nets: 29877 29720 *

Instances: 1265 1261 * MN (4 pins)
790 790 MP (4 pins)
5781 0 * _invb (6 pins)
10551 16326 * _invv (4 pins)
**************************************************************************************************************
INCORRECT OBJECTS
**************************************************************************************************************
LEGEND:
-------
ne = Naming Error (same layout name found in source
circuit, but object was matched otherwise).


NB:
1) If you added instance "_invb" and "_invv" in both layout and source, they have the same total
2) There is a huge difference between ports in layout and source, I think VDD and VSS ports of the std cells are the reason...but I don't know how to check this
I don't have experience to debug these errors, so can anyone tell me how to debug them ?

In Encounter, when I run this command "saveNetlist design.v -phys"
I get this warning: No Power/Ground connections in top module (design).

Pwr name (VDD).
Gnd name (VSS).
1 Pwr names and 1 Gnd names.
Creating all pg connections for top cell (design).


Can this be related to the LVS problem ?

That could be it. When you say there were zero geometry and connectivity violations in Encounter, are you sure you ran the checks at the top level?

For the Calibre issues, it is odd to have over 12,000 ports in the layout, and also odd that the top level port names are not valid for netlisting. These hint at a problem in the layer mapping. You may want to check the GDS to verify it looks like you intended.

If the GDS looks okay, can you compare the SPICE output from v2lvs to your layout in Encounter? If it doesn't pass, the problem may be in the v2lvs set up.

Good luck-

Sam.

slizak said:

That could be it. When you say there were zero geometry and connectivity violations in Encounter, are you sure you ran the checks at the top level?

For the Calibre issues, it is odd to have over 12,000 ports in the layout, and also odd that the top level port names are not valid for netlisting. These hint at a problem in the layer mapping. You may want to check the GDS to verify it looks like you intended.

If the GDS looks okay, can you compare the SPICE output from v2lvs to your layout in Encounter? If it doesn't pass, the problem may be in the v2lvs set up.

Good luck-

Sam.

Click to expand...

Thank you for your reply. The GDS is correctly imported in Virtuoso. I desperately tried to check one std cell of the Nangate 45nm library. So, I tried to run Calibre LVS on one std cell where I used its SPICE and GDS files provided with the library, but I got an error that the bulk of transistors in the layout is not connected to either VDD or VSS (see attached picture)....so this explains LVS error of the different number of nets in my original design.



As Nangate 45nm was developed using NCSU freePDK45nm, I used the Calibre LVS rule file provided with NCSU freePDK45nm since no calibre files were provided with Nangate. When I first run the LVS check using the Nangate 45nm std cell, I got this "ERROR: Rule file precision 2000 is not consistent with database precision 10000 in input file /root/Desktop/AES128bits/NangateOpenCellLibrary/Back_End/gds/AND2_X1.gds" so I went to LVS options and override layout precision to be 2000 as the rule file.

Can this be causing the problem ?

And for the different number of ports error in my original design LVS, I found that for large designs one should specify correspondence points. I didn't and I saw that only SOME of my I/O ports were included by default as correspondence points in LVS. If you know how to set these correspondence points, then please tell me.

Thanks

Correspondence points are influenced by the hcell list -- you don't want to list everything, or your run can get slow. nmLVS also matches on cells that have the same name. (Cell names may be influenced by your text layers, and based on your initial symptoms, your text layers may be misidentified in the SVRF file.) The exact matching algorithm depends on whether LVS was invoked with -automatch, -hcell, or both.

For more on the correspondence points, see the Calibre Verification User's Manual, especially "Initial Correspondence Points" and (if applicable) "Hcell Correspondence." Also, you can use Calibre Interactive (the GUI) to create a decent initial hcell list. Here's a Mentor Graphics video on how to do it: https://www.youtube.com/watch?v=Bhen3p_eKAA (You might also want to review their video list for other LVS topics, if videos are more to your taste than reading the manual.)

Best-

Sam.

slizak said:

Correspondence points are influenced by the hcell list -- you don't want to list everything, or your run can get slow. nmLVS also matches on cells that have the same name. (Cell names may be influenced by your text layers, and based on your initial symptoms, your text layers may be misidentified in the SVRF file.) The exact matching algorithm depends on whether LVS was invoked with -automatch, -hcell, or both.

For more on the correspondence points, see the Calibre Verification User's Manual, especially "Initial Correspondence Points" and (if applicable) "Hcell Correspondence." Also, you can use Calibre Interactive (the GUI) to create a decent initial hcell list. Here's a Mentor Graphics video on how to do it: https://www.youtube.com/watch?v=Bhen3p_eKAA (You might also want to review their video list for other LVS topics, if videos are more to your taste than reading the manual.)

Best-

Sam.

Click to expand...

Thank you for you. That helped me a lot !

What made me sure there is no problems with GDS transfer is that I didn't get any errors or warnings when importing my GDS in Virtuoso except for one warning that I didn't use a via map file and vias will be translated automatically and all metal layers and vias were translated with no warnings. I compared some metal layers between my original design in SoC Encounter and the imported layout in Virtuoso and they were all the same (didn't check vias though).

The std cell library didn't come with a layer map file, so I created my map file as stated below. I attached this map file during GDS export in Encounter and didn't use it in Virtuoso streamIn.

For example this is the streamOut.map file that is automatically generated by Encounter GDS export:
metal1 NET 49 0
metal1 SPNET 49 0
metal1 PIN 49 0
metal1 FILL 49 0
metal1 VIA 49 0
metal1 VIAFILL 49 0
NAME metal1/PIN 49 0
NAME metal1/SPNET 49 0

I changed it to be as follows (to match Virtuoso layer numbers) and attached it in GDS export in Encounter:

metal1 NET 11 0
metal1 SPNET 11 0
metal1 PIN 11 0
metal1 FILL 11 0
metal1 VIA 11 0
metal1 VIAFILL 11 0
NAME metal1/PIN 11 0
NAME metal1/SPNET 11 0

I then imported my layout in Virtuoso without the layer map file and didn't have errors or warnings.

So I should be sure that my layout in Virtuoso is correct, shouldn't I ?